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Programming method for non-volatile semiconductor memory device

  • US 6,587,381 B2
  • Filed: 09/19/2001
  • Issued: 07/01/2003
  • Est. Priority Date: 05/08/2001
  • Status: Expired due to Fees
First Claim
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1. A programming method for a non-volatile semiconductor memory device in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−

  • 1), (i), and (i+1) whose word gates are connected to one word line, data for the second non-volatile memory element of the twin memory cell (i) is programmed, said method comprising;

    setting the word line to a programming word line selection voltage;

    setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to a programming control gate voltage;

    setting the second control gate of the twin memory cell (i−

    1) and the first control gate of the twin memory cell (i) to an over-ride voltage;

    setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i) and the first non-volatile memory element of the twin memory cell (i+1) to a programming bit line voltage; and

    setting a bit line connected to the second non-volatile memory element of the twin memory cell (i+1) to a voltage higher than 0 V.

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