Programming method for non-volatile semiconductor memory device
First Claim
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1. A programming method for a non-volatile semiconductor memory device in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−
- 1), (i), and (i+1) whose word gates are connected to one word line, data for the second non-volatile memory element of the twin memory cell (i) is programmed, said method comprising;
setting the word line to a programming word line selection voltage;
setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to a programming control gate voltage;
setting the second control gate of the twin memory cell (i−
1) and the first control gate of the twin memory cell (i) to an over-ride voltage;
setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i) and the first non-volatile memory element of the twin memory cell (i+1) to a programming bit line voltage; and
setting a bit line connected to the second non-volatile memory element of the twin memory cell (i+1) to a voltage higher than 0 V.
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Abstract
A method is provided for programming data for a memory element of a twin memory cell (i). The word line WL1 is set to a programming word line selection voltage, the control gate CG[i+1] is set to a programming control gate voltage, and the control gate CG[i] is set to an over-ride voltage. The bit line BL[i+1] is set to a programming bit line voltage, and the bit line BL[i+2] is set to Vdd, but not to 0 V.
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Citations
10 Claims
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1. A programming method for a non-volatile semiconductor memory device in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−
- 1), (i), and (i+1) whose word gates are connected to one word line, data for the second non-volatile memory element of the twin memory cell (i) is programmed, said method comprising;
setting the word line to a programming word line selection voltage;
setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to a programming control gate voltage;
setting the second control gate of the twin memory cell (i−
1) and the first control gate of the twin memory cell (i) to an over-ride voltage;
setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i) and the first non-volatile memory element of the twin memory cell (i+1) to a programming bit line voltage; and
setting a bit line connected to the second non-volatile memory element of the twin memory cell (i+1) to a voltage higher than 0 V. - View Dependent Claims (2, 3, 4, 5)
- 1), (i), and (i+1) whose word gates are connected to one word line, data for the second non-volatile memory element of the twin memory cell (i) is programmed, said method comprising;
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6. A programming method for a non-volatile semiconductor memory device in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−
- 1), (i) and (i+1) whose word gates are connected to one word line, data for the first non-volatile memory element of the twin memory cell (i) is programmed, said method comprising;
setting the word line to a programming word line selection voltage;
setting the second control gate of the twin memory cell (i−
1) and the first control gate of the twin memory cell (i) to a programming control gate voltage;
setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to an over-ride voltage;
setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i−
1) and the first non-volatile memory element of the twin memory cell (i) to a programming bit line voltage; and
setting a bit line connected to the first non-volatile memory element of the twin memory cell (i−
1) to a voltage higher than 0 V.- View Dependent Claims (7, 8, 9, 10)
- 1), (i) and (i+1) whose word gates are connected to one word line, data for the first non-volatile memory element of the twin memory cell (i) is programmed, said method comprising;
Specification
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Current AssigneeSeiko Epson Corporation (Seiko Group)
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Original AssigneeHalo Lsi Design & Device Technology, Inc., Seiko Epson Corporation (Seiko Group)
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InventorsKanai, Masahiro, Kamei, Teruhiko
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Primary Examiner(s)NGUYEN, TAN
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Application NumberUS09/955,160Publication NumberTime in Patent Office650 DaysField of Search365/185.28, 365/185.18, 365/185.05, 365/185.25US Class Current365/185.28CPC Class CodesG11C 16/0458 comprising two or more inde...G11C 16/0475 comprising two or more inde...G11C 16/12 Programming voltage switchi...
