Phase detector architecture for phase error estimating and zero phase restarting

• US 6,587,529 B1
• Filed: 02/25/1999
• Issued: 07/01/2003
• Est. Priority Date: 02/25/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Spagna, Fulvio, Staszewski, Robert B.
• Primary Examiner(s): Corrielus, Jean
• Application Number:
  US09/258,827
• Time in Patent Office: 1,587 Days
• Field of Search: 375/371, 375/354, 375/355, 375/324, 375/325, 375/326, 375/327, 370/503, 360/51
• US Class Current: 375/371
• CPC Class Codes: G11B 20/10 Digital recording or reproducing
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10074 EPR4, i.e. extended partial response class 4, polynomial (1-D) *(1+D)2

Abstract

A system and method for enabling an efficient Zero Phase Restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks (501 and 502) in pairs, each circuit employing an orthogonal phase error transfer function characteristic (having one TG circuit sample orthogonally in relation to the other), for example, PR4 and EPR4 modes ideal sampling instances of a preamble. An NTG block (501 or 502) is selected based on having a native timing sampling instance with a phase error that is closest to zero. Since there is an equal chance that either of the circuits in a circuit pair will be selected, if the circuit implementing the current non-native architecture is selected, a separate signal is generated. This signal adds the equivalent of 180° to the error value that is provided to the timing recovery circuit. For example, by iterating the process after the special case of a zero phase restart (ZPR) operation, the native sampling instance is “forced” to be selected thereafter.

Claims

1. A method for estimating phase error when processing a digitized signal in a timing recovery circuit operable in a system associated with a memory and also incorporating a phase detector having an input and an output, comprising:

a) employing timing gradient circuits, one of said timing gradient circuits being a native gradient circuit and another of said timing gradient circuits being a non-native gradient circuit, each of said timing gradient circuits implementing a different phase error transfer characteristic;

b) normalizing, if necessary, each of said timing gradient circuits; and

c) estimating a phase adjustment operation;

wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuit, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, and

wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180°

is added to said value x.

2. The method of claim 1 further comprising iterating said steps b) and c) until fixing said value, x, wherein said value x is derived from a device outputting a number.

3. The method of claim 1 wherein said equivalent of 180°

is input as a state to the memory prior to being processed in an internal calculation.

4. The method of claim 1 wherein said equivalent of 180°

is input as a separate signal to the timing recovery circuit.

5. The method of claim 1 further comprising minimizing the phase error wherein adjustment of the phase is initiated.

6. The method of claim 5 further comprising iterating steps a through c for purposes of initiating a zero phase restart (ZPR).

7. The method of claim 5 further comprising providing said equivalent of 180°

as a separate signal to the timing recovery circuit for use in initiating a zero phase restart.

8. The method of claim 5 further comprising providing said equivalent of 180°

as a state to the memory prior to being processed in an internal calculation prior to use in a zero phase restart.

9. The method of claim 2 wherein said device calculates a minimum of the absolute value |min| of said adjustment value x, wherein |min| is fixed as an adjustment value.

10. The method of claim 2 wherein said device calculates x², the square of said adjustment value x, wherein x² is fixed as an adjustment value.

11. The method of claim 1 wherein said timing gradient circuits comprise a pair of timing gradient circuits, being mathematically described as maximally separated from each other, such that each of said timing gradient circuit has sampling instances orthogonal to sampling instances of other said timing gradient circuits.

12. The method of claim 11 wherein said orthogonality is obtained by the use of PRML encoding methods PR4 and EPR4, wherein either method is selected as the native timing gradient.

13. The method of claim 1 further enabling modulo/circular arithmetics if the phase detector output corresponds to an equivalent of 180°

, wherein adding the equivalent of 180°

involves inverting the MSB bit of the phase detector output.

14. A system incorporating a phase detector having an input and an output, a timing recovery circuit, and in association with a memory, comprising:

a native timing gradient circuit and a non-native timing gradient circuit, for

generating first and second outputs TG₀ and TG₁, respectively; and

a comparator for receiving said TG₀ and TG₁ and comparing values thereof,

wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuit, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, and

wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180°

is added to said adjustment value x.

15. The system of claim 14 wherein said equivalent of 180°

is input as a state to the memory for further processing prior to input to the timing recovery circuit.

16. The system of claim 14 wherein said equivalent of 180°

is input as a separate signal to the timing recovery circuit for further processing.

17. The system of claim 14 wherein said timing gradient circuits are provided as a pair, each circuit of said pair employing a native sampling instance orthogonal to the native sampling instance of the other of said timing gradient circuits.

18. The system of claim 14 wherein said equivalent of 180°

is input as a state to the memory for further processing prior to input to the timing recovery circuit for use in initiating a zero phase restart.

19. The system of claim 14 wherein said equivalent of 180°

is input as a separate signal to the timing recovery circuit for further processing prior to use in initiating a zero phase restart.

20. The system of claim 14 further enabling modulo/circular arithmetics, if the phase detector output corresponds to an equivalent of 180°

, wherein adding the equivalent of 180°

involves inverting the MSB bit of said phase detector output.

21. The system of claim 14 wherein said timing recovery circuit implements a phase-locked loop (PLL).

22. A phase detector, having an input and an output, and an association with a memory and a timing recovery circuit, comprising:

a native timing gradient circuit and a non-native timing gradient circuit, for generating first and second outputs TG₀ and TG₁, respectively; and

a comparator for receiving said TG₀ and TG₁ and comparing values thereof,

wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuits, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, and

wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180°

is added to said adjustment value x.

23. The phase detector of claim 22 wherein said equivalent of 180°

is input as a state to the memory for further processing prior to input to the timing recovery circuit.

24. The phase detector of claim 22 wherein said equivalent of 180°

is input as a separate signal to the timing recovery circuit for further processing.

25. The phase detector of claim 22 wherein said timing gradient circuits are provided as a pair, each circuit of said pair employing a native sampling instance orthogonal to the native sampling instance of the other of said timing gradient circuits.

26. The phase detector of claim 22 wherein said equivalent of 180°

is input as a state to the memory for further processing prior to input to the timing recovery circuit for use in initiating a zero phase restart.

27. The phase detector of claim 22 wherein said equivalent of 180°

is input as a separate signal to the timing recovery circuit for further processing prior to use in initiating a zero phase restart.

28. The phase detector of claim 22 further enabling modulo/circular arithmetics if the phase detector output corresponds to an equivalent of 180°

, wherein adding the equivalent of 180°

involves inverting the MSB bit of said phase detector output.

29. The phase detector of claim 22 wherein the timing recovery circuit implements a phase-locked loop (PLL).

30. A mass data storage system incorporating a phase detector having an input and an output, and an association with a memory and a timing recovery circuit, comprising:

a native timing gradient circuit and a non-native timing gradient circuit, for generating first and second outputs TG₀ and TG₁, respectively; and

a comparator for receiving said TG₀ and TG₁ and comparing values thereof,

wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuits, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, and

wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180°

is added to said adjustment value x.

31. The mass data storage system of claim 30 wherein said equivalent of 180°

is input as a state to the memory for further processing prior to input to the timing recovery circuit.

32. The mass data storage system of claim 30 wherein said equivalent of 180°

is input as a separate signal to the timing recovery circuit for further processing.

33. The mass data storage system of claim 30 wherein said timing gradient circuits are provided as a pair, each circuit of said pair employing a native sampling instance orthogonal to the native sampling instance of the other of said timing gradient circuits.

34. The mass data storage system of claim 30 wherein said equivalent of 180°

is input as a state to the memory for further processing prior to input to the timing recovery circuit for use in initiating a zero phase restart.

35. The mass data storage system of claim 30 wherein said equivalent of 180°

is input as a separate signal to the timing recovery circuit for further processing prior to use in initiating a zero phase restart.

36. The mass data storage system of claim 30 further enabling modulo/circular arithmetics if the phase detector output corresponds to an equivalent of 180°

, wherein adding the equivalent of 180°

involves inverting the MSB bit of said phase detector output.

37. The mass data storage system of claim 30 wherein the timing recovery circuit implements a phase-locked loop (PLL).

38. The mass data storage system of claim 30 wherein the mass storage system comprises a disk drive.