Galois field linear transformer

• US 6,587,864 B2
• Filed: 01/18/2002
• Issued: 07/01/2003
• Est. Priority Date: 11/30/2001
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Kablotsky, Joshua A., Stein, Yosef, Primo, Haim
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US10/051,533
• Publication Number:
  US 20030105790A1
• Time in Patent Office: 529 Days
• Field of Search: 708/492
• US Class Current: 708/492
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10

Abstract

A Galois field linear transformer includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includes a plurality of cells, each cell including an exclusive OR logic circuit and AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of the input bits and a programmable storage device for providing an input to its associated AND logic circuit for setting the matrix to obtain a multi-cycle Galois field linear transformation of the inputs in a single cycle.

Claims

1. A Galois field linear transformer comprising:

a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs for providing the Galois field linear transformation of those bits;

said matrix including a plurality of cells, each cell including an exclusive OR logic circuit, an AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of said input bits, and a programmable storage device for providing an input to its associated AND logic circuit for setting the matrix to obtain a multicycle Galois field linear transformation of the inputs in a single cycle.

2. The Galois field linear transformer of claim 1 in which each said exclusive OR gate has its output connected to the input of the next successive exclusive OR logic circuit except for the last exclusive OR logic circuit whose output is connected to the output of the matrix and the first exclusive OR logic circuit whose input is connected to a zero level.

3. The Galois field linear transformer of claim 1 in which said programmable storage device includes a number of storage units each one programmed for enabling a different Galois field linear transformation.

4. The Galois field linear transformer of claim 1 in which said inputs to said matrix include state inputs representative of previous state conditions of the Galois field linear outputs of the matrix.

5. The Galois field linear transformer of claim 4 in which said inputs to said matrix include state inputs fed back from the previous state conditions represented by the Galois field linear outputs of the matrix.