Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory

• US 6,587,894 B1
• Filed: 11/14/2000
• Issued: 07/01/2003
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Szabelski, Piotr, Stracovsky, Henry
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Nguyen, Tanh Q
• Application Number:
  US09/712,993
• Time in Patent Office: 959 Days
• Field of Search: 710/5, 710/6, 710/7, 710/20, 710/25, 710/29, 710/35, 710/36, 710/39, 710/40, 710/41, 710/43, 710/45, 710/52, 710/58, 710/59, 710/112, 710/115-118, 710/122-125, 710/244, 709/100, 709/102, 709/103, 709/104, 709/107, 709/207, 711/158, 711/167, 711/168, 711/169, 712/214-219
• US Class Current: 710/6
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1621 by maintaining request order
• CPC Class Codes: G06F 13/1626 by reordering requests

Abstract

According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus.

Claims

1. A method for reordering commands to achieve an optimal command sequence based on a target response restriction that determines an optimal slot for a data transfer between an initiator controller and a target subsystem by prohibiting an issuance of a command that would cause a data conflict, comprising:

at a command queue,

storing a command to be issued,

storing a time indicating when the data transfer appears on a data bus between the controller and the target device after the command was issued to the target,

storing a burst-bit indicating data burst transfer and a read/write bit (r/w);

in a data queue coupled to the command queue,

storing a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device, and

storing the burst bit and the read/write bit (r/w);

at a collision detector coupled to the data queue and the command queue,

detecting the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue;

storing target subsystem characterization data at a target subsystem characterization data base; and

at a queues and link controller coupled to the collision detector the data queue and the command queue,

reordering commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus, wherein the new issue time is based at least in part on the target subsystem characterization data, and

storing the reordered commands.

2. A method as recited in claim 1, wherein the target subsystem is a first one of a plurality of target subsystems.

3. A method as recited in claim 2, wherein the target subsystem characterization data base includes characterization data specific to each of the plurality of target subsystems.

4. A method as recited in claim 1, wherein the target subsystem is a memory device.

5. A method as recited in claim 4, wherein the memory device is a SLDRAM type memory device.

6. An apparatus for reordering commands to achieve an optimal command sequence based on a target response restriction that determines an optimal slot for a data transfer between an initiator controller and a target subsystem by prohibiting an issuance of a command that would cause a data conflict, comprising:

at a command queue,

a means for storing a command to be issued,

a means for storing a time indicating when the data transfer appears on a data bus between the controller and the target device after the command was issued to the target,

a means for storing a burst-bit indicating data burst transfer and a read/write bit (r/w);

in a data queue coupled to the command queue,

a means for storing a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device, and

a means for storing the burst bit and the read/write bit (r/w);

at a collision detector coupled to the data queue and the command queue,

a means for detecting the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue;

a means for storing target subsystem characterization data at a target subsystem characterization data base; and

at a queues and link controller coupled to the collision detector the data queue and the command queue,

a means for reordering commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus, wherein the new issue time is based at least in part on the target subsystem characterization data, and

a means for storing the reordered commands.

7. An apparatus as recited in claim 6, wherein the target subsystem is a first one of a plurality of target subsystems.

8. An apparatus as recited in claim 7, wherein the target subsystem characterization data base includes characterization data specific to each of the plurality of target subsystems.

9. An apparatus as recited in claim 6, wherein the target subsystem is a memory device.

10. An apparatus as recited in claim 9, wherein the memory device is a SLDRAM type memory device.