System and method for verification of off-chip processor code

• US 6,587,947 B1
• Filed: 04/01/1999
• Issued: 07/01/2003
• Est. Priority Date: 04/01/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Thangadurai, George, OʼDonnell, Amy, Rajan, Anand
• Primary Examiner(s): Darrow, Justin T.
• Application Number:
  US09/283,062
• Time in Patent Office: 1,552 Days
• Field of Search: 713/1, 713/100, 713/151, 713/161, 713/164, 713/167, 713/170, 713/172, 713/174, 713/187, 713/189, 713/200, 713/201, 713/202, 714/38, 705/65, 705/66, 705/67, 709/100, 712/277, 712/224
• US Class Current: 713/187
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures

Abstract

An electronic system and corresponding method for verifying the integrity of code that is stored off-chip. The electronic system comprises a memory element to store Processor Abstraction Layer (PAL) code and a processor coupled to the memory element. The processor verifies the integrity of the PAL code prior to execution of the PAL code.

Claims

1. An electronic system comprising:

a memory element to store Processor Abstraction Layer (PAL) code; and

a processor coupled to the memory element and including a first secret key, a second secret key, and a pre-computed message authentication code (MAC) value, the processor to verify the integrity of the PAL code prior to execution of the PAL code.

2. The electronic system of claim 1, wherein the verification of the PAL code occurs prior to releasing the processor from a RESET state.

3. The electronic system of claim 1, wherein the processor further includes a cyclic redundancy check message authentication code (CRC MAC) function.

4. The electronic system of claim 3, wherein the first secret key is an irreducible polynomial of degree N, where N is a positive whole number.

5. The electronic system of claim 4, wherein the second secret key is a random N-bit word.

6. The electronic system of claim 3, wherein the pre-computed MAC value includes a message digest being a result of a hash operation on the PAL code according to a selected hash function.

7. The electronic system of claim 6, wherein upon receiving the PAL code, the processor executes the CRC MAC function to produce a computed MAC value.

8. The electronic system of claims 7, wherein the PAL code is verified if the computed MAC value matches the pre-computed MAC value.

9. The electronic system of claim 1, wherein both the memory element and the processor are coupled to a substrate covered by a package, the substrate having a connector protruding from the package.

10. An electronic system comprising:

a first substrate; and

a processing unit coupled to the first substrate, the processing unit including

a second substrate,

a processor placed on the second substrate comprises a first secret key, a second secret key, and a pre-computed message authentication code (MAC) value, and

an on-substrate memory element coupled to the processor and placed on the second substrate, the on-substrate memory element containing Processor Abstract Layer (PAL) code having its integrity verified by the processor before execution of the PAL code and prior to releasing the processor from a RESET state.

11. The electronic system of claim 10, wherein the processor of the processing unit further includes a cyclic redundancy check message authentication code (CRC MAC) function.

12. The electronic system of claim 11, wherein the pre-computed MAC value includes a message digest being a result of a hash operation on the PAL code according to a selected hash function.

13. The electronic system of claim 12, wherein upon receiving the PAL code, the processor executes the CRC MAC function to produce a computed MAC value in order to verify that the PAL code has not been tampered when the computed MAC value matches the precomputed MAC value.

14. The electronic system of claim 10, wherein the first secret key is an irreducible polynomial of degree N and the second key is a random N-bit word, where N is a number having a factor of 2.

15. The electronic system of claim 10, wherein the processing unit is covered by a package with an edge connector of the second substrate protruding from the package.

16. An electronic system comprising:

memory means for storing Processor Abstraction Layer (PAL) code; and

processing means for verifying the integrity of the PAL code during a reset sequence before executing the PAL code the processing means including a first secret key, a second secret key, and a pre-computed message authentication code (MAC) value.

17. A method comprising:

loading code from a memory element to a local memory of a processor, the memory element is remotely situated from the processor;

performing a cyclic redundancy check message authentication code (CRC MAC) function on the code to produce a computed MAC value;

comparing the computed MAC value to a pre-computed MAC value prestored in the local memory of the processor; and

allowing the processor to execute the code if the computed MAC value matches the precomputed MAC value.

18. The method of claim 17 further comprising:

preventing the processor from executing the code if the computed MAC value fails to match the pre-computed MAC value.