Transparent software emulation as an alternative to hardware bus lock

• US 6,587,964 B1
• Filed: 02/18/2000
• Issued: 07/01/2003
• Est. Priority Date: 02/18/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Brooks, Robert J
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US09/504,023
• Time in Patent Office: 1,229 Days
• Field of Search: 714/28, 714/38, 714/43, 710/108, 703/28, 703/26
• US Class Current: 714/28
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.

Claims

1. A method for emulating hardware bus lock in a computer system, comprising:

acquiring a bus lock semaphore reserved for bus lock emulation;

acquiring a page table semaphore;

setting a mode bit that defeats fault-on-lock-attempt behavior;

invalidating relevant page table entries;

executing an instruction; and

releasing mode bit and the bus lock and page table semaphores.

2. The method of claim 1, further comprising purging translation lookaside buffers storing the relevant page table entries.

3. The method of claim 1, further comprising a mode bit that distinguishes between hardware bus lock and emulation of hardware bus lock.

4. The method of claim 1, further comprising locally inserting translation/protection entries.

5. The method of claim 1, wherein the computer system includes multiple computer architectures, and wherein a device requesting a bus lock is one of a central processing unit and an input/output device.

6. The method of claim 1, wherein the instruction to be executed is an instruction that requested the bus lock.

7. The method of claim 1, wherein the instruction to be executed is a clone routine without the bus lock semantics.

8. The method of claim 1, wherein the instruction is an original instruction causing the bus fault.

9. A method for emulating a hardware bus lock in a computer system, comprising:

receiving a hardware bus lock request from a device in the computer system;

generating a fault in response to the hardware bus lock request;

setting a mode bit that defeats fault-on-lock-attempt behavior, thereby preventing a hardware bus lock;

processing the fault in a fault handler; and

releasing the mode bit after the processing.

10. The method of claim 9, further comprising:

setting a first semaphore for bus lock emulation;

setting a second semaphore to limit page access; and

after the processing step, releasing the first and the second semaphores.

11. An apparatus for emulating hardware bus lock in a computer system, comprising:

a fault handler that, in response to a device requesting a hardware bus lock, acquires a bus lock semaphore and a page table semaphore; and

an emulation module coupled to the fault handler that invalidates entries in a page table, wherein the fault handler sets a mode bit that defeats fault-on-lock-attempt behavior to prevent hardware bus lock, releases the mode bit and the semaphores after execution of an instruction by the device.

12. The apparatus of claim 11, wherein the bus lock semaphore and the page table semaphore are cacheable.

13. The apparatus of claim 11, wherein the instruction is an original instruction that caused the bus fault.

14. The apparatus of claim 11, wherein the instruction is a clone instruction or clone instruction sequence.