Semiconductor test apparatus and method

• US 6,587,975 B2
• Filed: 07/01/1999
• Issued: 07/01/2003
• Est. Priority Date: 01/25/1999
• Status: Expired due to Term

• Current Assignee: Renesas Semiconductor Manufacturing Co. Ltd. (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Ryoden Semiconductor System Engineering Corporation
• Inventors: Mori, Hisaya, Funakura, Teruhiko
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Torres, Joseph D.
• Application Number:
  US09/346,268
• Publication Number:
  US 20030070121A1
• Time in Patent Office: 1,461 Days
• Field of Search: 714/723, 714/710, 714/711, 365/201, 365/200
• US Class Current: 714/723
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A semiconductor test apparatus and method for performing a test on a nonvolatile semiconductor memory such as a flash memory while preventing excessive erasing with reliability. In each erase operation, all addresses are scanned to fetch an error address and error data into a catch memory. Then, on the basis of error information (error address and error data), a rewrite operation is performed to write data on all memory cells. The write data varies according to a comparison result between an address signal and an error address signal. If they disagree, a “0” is written on a memory cell at the address. If they agree, a “0” is written on a “pass” memory cell and a “1” is virtually written on a fail memory cell.

Claims

1. A semiconductor test apparatus comprising:

a control signal generating unit configured to supply a control signal to at least one semiconductor memory under test so as to initiate a predetermined operation, said at least one semiconductor memory under test having a plurality of cells, said predetermined operation including an erase operation of setting each of said plurality of cells to a first value and a subsequent rewrite operation of setting a subset of said plurality of cells to a second value different from the first value;

a judging unit configured to make a pass/fail judgment on each of said plurality of cells after said erase operation, where a cell having been set to said first value is judged as having passed and a cell not having been set to said first value is judged as having failed; and

an error information storage unit configured to sequentially assign a semiconductor memory test address corresponding to each of said plurality of cells and to store a plurality of semiconductor memory test results, said semiconductor memory test results including a semiconductor memory error address corresponding to a cell judged by said judging unit as having failed, and corresponding error data, wherein

said subset of said plurality of cells comprising a cell judged by said judging unit as having passed.

2. The semiconductor test apparatus according to claim 1, further comprising:

an address generating unit configured to sequentially generate a semiconductor memory generated-test address, wherein

said error information storage unit includes a test address selecting portion configured to select either said semiconductor memory generated-test address or said semiconductor memory error address as a test address given to said semiconductor memory under test.

3. The semiconductor test apparatus according to claim 2, further comprising:

a test data generating unit configured to generate test data for said at least one semiconductor memory under test on the basis of contents of a test content switching signal;

a test control unit configured to stop, upon receipt of a test operation stop signal, a test on one of said at least one semiconductor memory under test without stopping a test on another of said at least one semiconductor memory under test, wherein

said error information storage unit stores a number of fetched error addresses and a plurality of semiconductor error addresses each corresponding to one of said at least one semiconductor memory under test, and

said error information storage unit includes a plurality of error information storage portions, each of said plurality of error information storage portions configured to store a corresponding semiconductor memory error address, to determine a test output end, and to generate said test operation stop signal and said test content switching signal.

4. The semiconductor test apparatus according to claim 3, wherein

said test content switching signal indicates switching the contents of a test on the basis of a comparison result between said semiconductor memory generated-test address and said semiconductor memory error address.

5. The semiconductor test apparatus according to claim 1, further comprising:

a first data generating unit configured to generate first data for each semiconductor memory test address, wherein

said error information storage unit includes a data arithmetic portion configured to process said first data with said corresponding error data to obtain a second data and a test value supplying portion configured to supply one of said first data and said second data to said at least one semiconductor memory under test.

6. The semiconductor test apparatus according to claim 5, wherein said error information storage unit further includes:

a selection signal output portion configured to output a selection signal on the basis of a comparison result between said semiconductor memory generated-test address and said semiconductor memory error address, wherein

said data arithmetic portion is configured to obtain said second data by an operation based on said selection signal.

7. The semiconductor test apparatus according to claim 1, further comprising:

a test control unit configured to stop, upon receipt of a test operation forced stop signal, a test on one of said at least one semiconductor memory under test, without stopping a test on another of said at least one semiconductor memory under test, wherein

said error information storage unit stores a number of fetched error addresses and a plurality of error addresses each corresponding to one of said at least one semiconductor memory under test, and

said error information storage unit includes a plurality of error information storage portions, each of said plurality of error information storage portions configured to store a corresponding error address and to generate said test operation stop signal if a number of error addresses is more than a predetermined number.

8. A semiconductor test method configured to determine whether a semiconductor memory has been successfully erased by a semiconductor test apparatus, including

a control signal generating unit configured to supply a control signal to at least one semiconductor memory under test so as to initiate a predetermined operation, said at least one semiconductor memory under test having a plurality of cells, said predetermined operation including an erase operation of setting each of said plurality of cells to a first value and a subsequent rewrite operation of setting a subset of said plurality of cells to a second value,

a judging unit configured to make a pass/fail judgement on each of said plurality of cells after said erase operation, where a cell having been set to said first value or successfully erased is judged as having passed and a cell not having been set to said first value or not having been successfully erased is judged as having failed, and

an error information storage unit configured to sequentially assign a semiconductor memory test address corresponding to each of said plurality of cells and to store a plurality of semiconductor memory test results, said semiconductor memory test results including a semiconductor memory error address corresponding to a cell judged by said judging unit as having failed and corresponding error data,

said semiconductor test method comprising the steps of:

(a) performing said erase operation;

(b) determining whether each of said plurality of cells was set to said first value so as to identify one of a successfully-erased cell and an unsuccessfully-erased cell;

(c) storing said plurality of semiconductor memory test results; and

(d) performing said rewrite operation only on said subset of said plurality of cells judged to have been successfully erased.

9. The semiconductor test method according to claim 8, further comprising:

(e) immediately after said step (c), judging whether all of said plurality of cells have been successfully erased, and if so, terminating an erase test and if not, performing said step (a) again, wherein

a first execution of said step (c) is performed on all of said plurality of memory cells, and a second and later executions of said step (c) is performed on, out of said plurality of cells, only a cell corresponding to said semiconductor memory error address in the next previous execution.

10. The semiconductor test method according to claim 9, wherein

in said step (e), said erase test is also terminated if a number of times that all of said plurality of cells are judged as not having been successfully erased exceeds a predetermined number of times.

11. The semiconductor test method according to claim 10, wherein

said semiconductor memory test results contain total error information including the number of fetched error addresses, and

said steps (a) through (d) of said erase test are performed independently for each of said at least one semiconductor memory under test,

said semiconductor test method further comprising the step of:

(f) making a pass/fail judgement on said at least one semiconductor memory under test on the basis of said total error information, and if said at least one semiconductor memory under test is judged as having failed, forcefully stopping every processing of said erase test on said at least one semiconductor memory,

said step (f) being performed after completion of said erase test on said at least one semiconductor memory under test in said step (e).

12. The semiconductor teat method according to claim 8, further comprising the steps of:

(g) obtaining a specified address of said at least one semiconductor memory under test;

(h) determining whether said specified address agrees with said semiconductor memory error address, and if so, obtaining said error data from said error information storage unit;

(i) performing a rewrite operation of setting a cell corresponding to said specified address to said second value; and

(j) repeating said steps (g) through (i) while incrementing said specified address for each address, and immediately after completion of the repetition of said steps (g) through (i), terminating the test if all of said plurality of cells has been successfully erased, and if not, performing said step (a) again.

13. A semiconductor test method configured to determine whether a semiconductor memory has been successfully erased by a semiconductor test apparatus, including

a control signal generating unit configured to supply a control signal to at least one semiconductor memory under test so as to initiate a predetermined operation, said at least one semiconductor memory under test having a plurality of cells, said predetermined operation including an erase operation of setting each of said plurality of cells to a first value and a subsequent rewrite operation of setting a subset of said plurality of cells to a second value different from the first value said subset of said plurality of cells being a set of cells judged by said judging unit as having passed,

a judging unit configured to make a pass/fail judgment on each of said plurality of cells after said erase operation, where a cell having been set to said first value is judged as having passed and a cell not having been set to said first value is judged as having failed, and

an error information storage unit configured to sequentially assign a semiconductor memory test address corresponding to each of said plurality of cells and to store a plurality of semiconductor memory test results, said semiconductor memory test results including a semiconductor memory error address corresponding to a cell judged by said judging unit as having failed, corresponding error data, and total error information including a number of fetched error addresses,

said semiconductor test method comprising the steps of:

(a) performing said erase operation;

(b) acquiring said total error information from said error information storage unit;

(c) making a pass/fail judgment on said at least one semiconductor memory under test on the basis of said total-error information; and

(d) writing information about said semiconductor memory error address into said at least one semiconductor memory under test if said at least one semiconductor memory under test is judged to have passed in said step (c).