Circuit and method for varying a pulse width of an internal control signal during a test mode

• US 6,587,978 B1
• Filed: 02/20/1996
• Issued: 07/01/2003
• Est. Priority Date: 02/14/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Casper, Stephen L., Merritt, Todd A., Raad, George B.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US08/603,943
• Time in Patent Office: 2,688 Days
• Field of Search: 371/21.1, 371/21.4, 371/21.5, 365/189.01, 365/200-201, 365/189.05, 365/193, 364/265.3, 395/183.01, 395/183.03, 395/183.06, 711/155, 711/156, 713/400, 714/718, 714/721, 714/722, 714/15, 714/25, 714/39, 714/46, 714/48, 714/724, 714/42, 714/44, 714/45, 707/202
• US Class Current: 714/718
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/50012 of timing

Abstract

The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a pulse width of an internal control signal to stress the DRAM during a test mode.

Claims

1. An electrical device having a circuit function during a normal operation mode, said electrical device fabricated on a supporting substrate, said electrical device comprising:

a) a first internal circuit for generating a first internal RAS signal having a pulse width in response to an external RAS signal, said electrical device performing the circuit function in response to said first internal RAS signal; and

b) a second internal circuit for generating an internal test signal in response to an external test signal, said second internal circuit in electrical communication with said first internal circuit, wherein a value of said pulse width of said first internal RAS signal varies during a test mode from a value of said pulse width during the normal operation mode in response to said internal test signal.

2. The electrical device as specified in claim 1, wherein said first internal circuit comprises:

a) a first delay circuit having a first delay circuit output signal;

b) a second delay circuit having a second delay circuit output signal; and

c) a multiplexer circuit responding to said internal test signal to multiplex said first delay circuit output signal to an output node of said first internal circuit as said internal RAS signal during said test mode and responding to said internal test signal to multiplex said second delay circuit output signal to said output node of said first internal circuit as said internal RAS signal during said normal operation mode.

3. A monolithic memory device for storing electrical data, comprising:

a) a means for generating an internal RAS signal having a pulse, said memory device performing a normal operation circuit function in response to said RAS signal in a normal operation mode; and

b) a means for varying a value of a pulse width of said pulse during a testing of a performance of said normal operation circuit function from a value of said pulse width during said normal operation mode.

4. The memory device as specified in claim 3, wherein the memory device is a dynamic random access memory device.

5. A memory device for storing data, the memory device being responsive to an external RAS signal and an external test signal, comprising:

a) an internal lockout circuit for generating an internal RAS signal having a pulse in response to said external RAS signal, said pulse of said internal RAS signal meeting a minimum pulse width circuit requirement during normal operation of the memory device regardless of a pulse width of a corresponding pulse of said external RAS signal; and

b) an internal test key circuit in electrical communication with said internal lockout circuit, said internal test key circuit responding to said external test signal to provide a test key signal, said internal lockout circuit responding to said test key signal during a test mode to decrease said pulse width of said pulse of said internal RAS signal in order to stress the memory device during a test mode.

6. The memory device as specified in claim 5, wherein said lockout circuit comprises:

a) a first delay circuit for delaying a transition of the internal RAS signal in response to a transition of the external RAS signal, an output signal of said first delay circuit being said internal RAS signal during the test mode; and

b) a second delay circuit for causing a further delay in said transition of the internal RAS signal, an output signal of said second delay circuit being said internal RAS signal during the normal operation of said memory device.

7. The memory device as specified in claim 6, wherein said internal lockout circuit comprises a multiplexer circuit responding to said test key signal to select said output signal of said first delay circuit during the test mode and responding to said test key signal to select said output signal of said second delay circuit during said normal operation, an output of said multiplexer circuit being said internal RAS signal.

8. The memory device as specified in claim 7, wherein said internal test key circuit comprises a latch circuit for latching said test key signal to a control input of said multiplexer circuit.

9. A monolithic memory device for storing data, comprising:

a) a lockout means for locking out effects of an external RAS signal thereby increasing a value of a pulse width of a pulse of an internal RAS signal from a value of a pulse width of a corresponding pulse of said external RAS signal during a normal operation of the monolithic memory device; and

b) an internal testing means for decreasing the value of the pulse width of the internal RAS signal during a test mode from the value of the pulse width of the pulse of the internal RAS signal during the normal operation.

10. A method of operating an encapsulated memory device, comprising the following steps:

a) generating an internal RAS signal in the encapsulated memory device;

b) performing a memory circuit function during a normal operation of the memory device in response to said internal RAS signal;

c) generating a test signal in the encapsulated memory device;

d) varying a pulse width of a pulse of said internal RAS signal in response to said test signal in order to stress the memory device; and

e) testing said memory circuit function during said step of varying.

11. The method as specified in claim 10, further comprising the step of decreasing said pulse width during said step of varying.

12. The method as specified in claim 10, wherein the method further comprises the following steps:

a) providing said internal RAS signal in response to an external RAS signal;

b) delaying a transition of said internal RAS signal in response to a transition of the external RAS signal during said step of providing thereby increasing a value of said pulse width of said pulse of said internal RAS signal from a value of a pulse width of a corresponding pulse of said external RAS signal, said step of delaying performed during the normal operation of the memory device; and

c) decreasing the value of said pulse width of said pulse of said internal RAS signal during said test mode from said value of said pulse width of said pulse of said internal RAS signal during the normal operation of the memory device.

13. The method as specified in claim 10, further comprising delaying a transition of an external RAS signal to generate a first delayed signal in the encapsulated memory device, wherein said first delayed signal is said internal RAS during said step of testing.

14. The method as specified in claim 13, further comprising delaying a transition of said first delayed signal to generate a second delayed signal in the encapsulated memory device, wherein said second delayed signal is said internal RAS signal during said step of performing.

15. The method as specified in claim 14, wherein said step of generating comprises multiplexing said first delayed signal and said second delayed signal to an internal node of said encapsulated memory device, said first and said second delayed signals functioning as said internal RAS signal.

16. The method as specified in claim 15, further comprising latching said test signal to a control input of said multiplexer circuit.

17. A method for operating an encapsulated electrical device, comprising the following steps:

a) internally generating in the electrical device an internal RAS signal having a pulse having a pulse width during a normal operation mode; and

b) varying a value of the pulse width of said pulse of said internal RAS signal during a test mode.

18. A method for operating an encapsulated electrical device, comprising the following steps:

a) accepting an external RAS signal as an input of the electrical device;

b) internally generating an internal RAS signal having a pulse in response to said external RAS signal, said pulse of said internal RAS signal meeting a minimum pulse width circuit requirement during a normal operation of the electrical device regardless of a pulse width of a corresponding pulse of said external RAS signal; and

c) accepting an external test signal;

d) providing an internal test key signal in response to said internal test signal; and

e) decreasing said pulse width of said pulse of said internal RAS signal during a test mode.

19. A method for operating an encapsulated electrical device, comprising the following steps:

a) locking out effects of an external RAS signal;

b) increasing a value of a pulse width of a pulse of an internal RAS signal from a value of a pulse width of a corresponding pulse of said external RAS signal during a normal operation of the electrical device in response to said step of locking out; and

c) decreasing the value of the pulse width of the internal RAS signal during a test mode from the value of the pulse width of the pulse of the internal RAS signal during the normal operation.