Enhanced programmable core model with integrated graphical debugging functionality

• US 6,587,995 B1
• Filed: 04/19/2000
• Issued: 07/01/2003
• Est. Priority Date: 04/19/2000
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Oddoart, Romain, Duboc, Jean Francois
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/552,395
• Time in Patent Office: 1,168 Days
• Field of Search: 716/4, 716/18, 716/3, 716/7, 703/16, 703/28
• US Class Current: 716/106
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An apparatus, program product and method incorporate into an enhanced programmable core model an embedded debug monitor to provide integrated graphical debugging functionality in the model. The debug monitor supports the performance of one or more debug operations on the programmable core model during simulation thereof. In addition, the debug monitor is configured to receive a debug parameter from a user through a graphical user interface, and report a result of the debug operation to a user via the graphical user interface. Through the use of a graphical user interface, interaction with a user is greatly facilitated. Moreover, by embedding the debug monitor within the programmable core model, a completely integrated simulation and debug environment may be provided to a user, with debugging functionality similar to that available to software developers and hardware-based processor designers. As a result, validation of a model'"'"'s performance can be performed more efficiently and with less effort.

Claims

1. A computer-implemented method of debugging a programmable core in an integrated circuit design, the method comprising:

(a) performing simulation on a programmable core model that functionally emulates the programmable core, the programmable core model including an event-driven debug monitor embedded therein;

(b) setting a debug parameter for the debug monitor in response to user input received through a graphical user interface;

(c) performing a debug operation with the debug monitor during simulation of the programmable core model; and

(d) reporting a result of the debug operation to a user via the graphical user interface.

2. The method of claim 1, wherein the debug operation is selected from a group consisting of a single-step operation, a multi-step operation, a register display operation, a disassemble operation, a trace operation, a breakpoint operation, a message display operation, a mode display operation, and combinations thereof.

3. The method of claim 1, further comprising executing a debug graphical user interface script to generate a parameter window on a computer display, wherein setting the debug parameter includes receiving user input directed to the parameter window.

4. The method of claim 3, wherein the debug monitor is configured to activate the debug graphical user interface script during initialization of the debug monitor.

5. The method of claim 3, further comprising establishing a communication channel between the debug monitor and the debug graphical user interface script, wherein setting the debug parameter includes transmitting the debug parameter from the graphical user interface script to the debug monitor over the communication channel, and wherein reporting the result of the debug operation includes transmitting the result from the debug monitor to the graphical user interface script over the communication channel.

6. The method of claim 5, wherein the communication channel includes a plurality of pipelines.

7. The method of claim 5, further comprising generating at least one of a message, register, and disassembler window, wherein reporting the result of the debug operation further includes displaying the result in one of the message, register and disassembler windows.

8. The method of claim 1, wherein performing the debug operation includes detecting a clock cycle start event that occurs during performance of the simulation and performing the debug operation responsive to the clock cycle start event.

9. The method of claim 1, wherein the programmable core model is a first programmable core model and the debug monitor is a first debug monitor, the method further comprising:

(a) assigning a first instance identifier to the first programmable core model;

(b) performing simulation on a second programmable core model associated with a second instance identifier concurrently with performing simulation on the first programmable core model, the second programmable core model including a second debug monitor;

(c) performing a debug operation on the second programmable core model with the second debug monitor during performance of the simulation on the second programmable core model; and

(d) reporting a result of the second debug operation to the user via the graphical user interface.

10. The method of claim 1, wherein performing the debug operation includes capturing state information from the programmable core model at a predetermined time during the simulation using the debug monitor.

11. The method of claim 10, wherein capturing the state information includes capturing at least one of a register value, a current instruction, a message, and a processor mode.

12. An apparatus, comprising:

(a) a memory;

(b) a programmable core model resident in the memory, the programmable core model configured to functionally emulate a programmable core in an integrated circuit design; and

(c) a program comprising an event-driven debug monitor embedded in the programmable core model, the program configured to simulate the programmable core model, set a debug parameter for the debug monitor in response to user input received through a graphical user interface, perform a debug operation with the debug monitor during simulation of the programmable core model, and report a result of the debug operation to a user via the graphical user interface.

13. The apparatus of claim 12, wherein the debug operation is selected from a group consisting of a single-step operation, a multi-step operation, a register display operation, a disassemble operation, a trace operation, a breakpoint operation, a message display operation, a mode display operation, and combinations thereof.

14. The apparatus of claim 12, wherein the program further comprises a simulator.

15. The apparatus of claim 12, wherein the program further comprises a debug graphical user interface script configured to generate a parameter window on a computer display, wherein the program is configured to set the debug parameter by receiving user input directed to the parameter window and transmitting the debug parameter to the debug monitor.

16. The apparatus of claim 15, wherein the debug monitor is configured to activate the debug graphical user interface script during initialization of the debug monitor.

17. The apparatus of claim 15, wherein the program is further configured to establish a communication channel between the debug monitor and the debug graphical user interface script, wherein the program is configured to set the debug parameter further by transmitting the debug parameter from the graphical user interface script to the debug monitor over the communication channel, and to report the result of the debug operation by transmitting the result from the debug monitor to the graphical user interface script over the communication channel.

18. The apparatus of claim 17, wherein the communication channel includes a plurality of pipelines.

19. The apparatus of claim 17, wherein the program is further configured to generate at least one of a message, register, and disassembler window, and to report the result of the debug operation further by displaying the result in one of the message, register and disassembler windows.

20. The apparatus of claim 12, wherein the program is configured to perform the debug operation by detecting a clock cycle start event that occurs during performance of the simulation and performing the debug operation responsive to the clock cycle start event.

21. The apparatus of claim 12, wherein the programmable core model is a first programmable core model associated with a first instance identifier and the debug monitor is a first debug monitor, the apparatus further comprising a second programmable core model associated with a second instance identifier and including a second debug monitor, wherein the program is further configured to concurrently simulate the first and second programmable core models and perform a second debug operation on the second programmable core model with the second debug monitor during the simulation.

22. The apparatus of claim 12, wherein the program is configured to perform the debug operation by capturing state information from the programmable core model at a predetermined time during the simulation using the debug monitor.

23. The apparatus of claim 22, wherein the program is configured to capture the state information by capturing at least one of a register value, a current instruction, a message, and a processor mode.

24. A program product, comprising:

(a) a programmable core model configured to functionally emulate a programmable core in an integrated circuit design, the programable core model including an event-driven debug monitor embedded therein, the debug monitor configured to receive a debug parameter from a user through a graphical user interface, perform a debug operation during simulation of the programmable core model, and report a result of the debug operation to a user via the graphical user interface; and

(b) a signal bearing medium bearing the programmable core model.

25. The program product of claim 24, wherein the signal bearing medium includes at least one of a transmission medium and a recordable medium.

26. The program product of claim 24, wherein the debug operation is selected from a group consisting of a single-step operation, a multi-step operation, a register display operation, a disassemble operation, a trace operation, a breakpoint operation, a message display operation, a mode display operation, and combinations thereof.

27. The program product of claim 24, wherein the programmable core model is configured to be executed on a simulator.

28. The program product of claim 24, wherein the debug monitor is configured to activate a debug graphical user interface script during initialization of the debug monitor.

29. The program product of claim 28, wherein the debug monitor is further configured to establish a communication channel between the debug monitor and the debug graphical user interface script.

30. The program product of claim 24, the debug monitor is configured to perform the debug operation by detecting a clock cycle start event that occurs during performance of the simulation and performing the debug operation responsive to the clock cycle start event.

31. The program product of claim 30, wherein the debug monitor is configured to perform the debug operation by capturing state information from the programmable core model at a predetermined time during the simulation.

32. The program product of claim 31, wherein the debug monitor is configured to capture the state information by capturing at least one of a register value, a current instruction, a message, and a processor mode.

33. The program product of claim 24, wherein the programmable core model further comprises:

(a) a compiled netlist emulating the functionality of the programmable core in a simulator-generic representation;

(b) a simulator shell encapsulating the compiled netlist and the debug monitor and configured to interface the compiled netlist and the debug monitor with the simulator; and

(c) a timing shell encapsulating the simulator shell and providing timing data for use by the simulator in simulating the programmable core.

34. The program product of claim 33, wherein the compiled netlist and debug monitor are defined in a c programming language.