Modeling delays for small nets in an integrated circuit design

• US 6,587,999 B1
• Filed: 05/15/2001
• Issued: 07/01/2003
• Est. Priority Date: 05/15/2001
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Chen, Lei, Zhang, Nianging, Bhutani, Sandeep
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Vu, Quang
• Application Number:
  US09/859,149
• Time in Patent Office: 777 Days
• Field of Search: 716/4-6, 716/10-13, 716/16-18
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.

Claims

1. A method of modeling cell delays in an integrated circuit design comprising the steps of:

(a) receiving as input a description of an integrated circuit design;

(b) identifying at least one small net in the integrated circuit design from the description;

(c) approximating an effective capacitance of the at least one small net by a total capacitance; and

(d) approximating an interconnect delay of the at least one small net by zero.

2. The method of claim 1 wherein step (b) comprises comparing a ratio of a driver resistance to a wire resistance of each of a plurality of nets in the integrated circuit design with a selected minimum ratio.

3. The method of claim 2 wherein the selected minimum ratio is substantially equal to nine.

4. The method of claim 2 wherein step (b) comprises comparing a product of the wire resistance times a total capacitance of each of the plurality of nets in the integrated circuit design with a selected minimum wire delay.

5. The method of claim 4 wherein the selected minimum wire delay is substantially equal to one picosecond.

6. The method of claim 4 further comprising the step of (e) calculating a cell delay from the effective capacitance of the at least one small net.

7. The method of claim 6 further comprising the step of (f) calculating a cell delay and an interconnect delay for at least one large net in the plurality of nets in the integrated circuit design wherein the at least one large net is one of the plurality of nets not identified as the at least one small net.

8. The method of claim 7 further comprising the step of (g) generating as output the interconnect delay calculated for the at least one small net and the interconnect delay calculated for the at least one large net in a Standard Delay Format file.

9. A computer program product comprising:

a medium for embodying a computer program for input to a computer; and

a computer program embodied in the medium for causing the computer to perform at least one of the following functions;

(a) receiving as input a description of an integrated circuit design;

(b) identifying at least one small net in the integrated circuit design from the description;

(c) approximating an effective capacitance of the at least one small net by a total capacitance; and

(d) approximating an interconnect delay of the at least one small net by zero.

10. The computer program product of claim 9 wherein step (b) comprises comparing a ratio of a driver resistance to a wire resistance for each of a plurality of nets in the integrated circuit design with a selected minimum ratio.

11. The computer program product of claim 10 wherein the selected minimum ratio is substantially equal to nine.

12. The computer program product of claim 10 wherein step (b) comprises comparing a product of the wire resistance times a total capacitance for each of the plurality of nets in the integrated circuit design with a selected minimum wire delay.

13. The computer program product of claim 12 wherein the selected minimum wire delay is substantially equal to one picosecond.

14. The computer program product of claim 12 further comprising the step of (e) calculating a cell delay from the effective capacitance of the at least one small net.

15. The computer program product of claim 14 further comprising the step of (f) calculating a cell delay and an interconnect delay for at least one large net in the plurality of nets in the integrated circuit design wherein the at least one large net is one of the plurality of nets not identified as the at least one small net.

16. The computer program product of claim 15 further comprising the step of (g) generating as output the interconnect delay and the cell delay calculated for the at least one small net and the interconnect delay and the cell delay calculated for the at least one large net in a Standard Delay Format file.

17. A method of modeling cell delays in an integrated circuit design comprising the steps of:

(a) receiving as input a description of an integrated circuit design;

(b) calculating a wire resistance for each of a plurality of nets from the description;

(c) calculating a total capacitance for each of the plurality of nets;

(d) identifying a plurality of small nets in the plurality of nets;

(e) approximating an effective capacitance for each of the plurality of small nets by the total capacitance;

(f) approximating an interconnect delay for each of the plurality of small nets by zero; and

(g) calculating a cell delay from the interconnect delay and the effective capacitance for each of the plurality of small nets.

18. The method of claim 17 wherein step (b) comprises comparing a ratio of a driver resistance to a wire resistance for each of the plurality of nets with a selected minimum ratio.

19. The method of claim 18 wherein the selected minimum ratio is substantially equal to nine.

20. The method of claim 18 wherein step (b) comprises comparing a product of the wire resistance times a total capacitance for each of the plurality of nets with a selected minimum wire delay.

21. The method of claim 20 wherein the selected minimum wire delay is substantially equal to one picosecond.

22. The method of claim 20 further comprising the step of (h) calculating a cell delay and an interconnect delay for a plurality of large nets in the plurality of nets wherein each of the plurality of large nets is not identified as one of the plurality of small nets.

23. The method of claim 22 further comprising the step of (i) generating as output the interconnect delay and the cell delay calculated for each of the plurality of small nets and for each of the plurality of large nets in a Standard Delay Format file.