Graphic editor for block diagram level design of circuits

• US 6,588,004 B1
• Filed: 07/07/2000
• Issued: 07/01/2003
• Est. Priority Date: 10/28/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Southgate, Timothy J., Wenzler, Michael
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/611,376
• Time in Patent Office: 1,089 Days
• Field of Search: 716/1-18, 703/14-16
• US Class Current: 716/102
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 8/60 Software deployment
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06Q 10/06 Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
• CPC Class Codes: G06Q 10/10 Office automation; Time management
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99954 Version management

Abstract

A method is described herein for designing a circuit using graphic editor software. A graphic design file is generated corresponding to a block diagram created in a graphical user interface associated with the graphic editor software. The block diagram includes a plurality of blocks and a plurality of conduits interconnecting the blocks. A block design file is generated in one of a plurality of formats for each of selected ones of the plurality of blocks in the block diagram. Each of the block design files corresponds to an implementation of its corresponding block. Modifications to any of the graphic design file and the block design files are incorporated into each other under software control.

Claims

1. A method for designing a circuit using graphic editor software, comprising:

generating a first graphic design file, created in a graphical user interface associated with the graphic editor software, by importing one or more fully specified or partially specified block design files in one of a plurality of formats; and

generating a first block diagram, the first block diagram comprising a plurality of blocks and a plurality of conduits interconnecting the blocks, wherein at least one of the blocks corresponds to at least one of the fully specified or partially specified block design files,

wherein modifications to any of the first graphic design file and the block design files are incorporated into each other under software control.

2. The method of claim 1, wherein generating the first graphic design file further comprises:

determining the blocks with unassigned I/O in the first block diagram;

assigning I/O to each of the blocks with unassigned I/O in the first block diagram;

assigning at least one signal name for each conduit in the first block diagram, and

determining correspondence between the I/O and the at least one signal name.

3. The method of claim 1, wherein generating the first graphic design file further comprises:

assigning external I/O to the first block diagram.

4. The method of claim 3, wherein the external I/O corresponds to a pin out of a chip.

5. The method of claim 3, wherein the external I/O is a connection to a second block diagram with a second hierarchy level different from a first hierarchy level of the first block diagram.

6. The method of claim 1, wherein the plurality of formats includes at least one text format.

7. The method of claim 1, wherein selected ones of the conduits each represent a plurality of bi-directional signal paths.

8. The method of claim 1, wherein said one or more fully specified or partially specified block design files respectively specify a fill implementation or a partial implementation of one or more blocks.

9. The method of claim 1, wherein generating the block design file further comprises:

selecting one block design file from the imported partially specified block design files;

selecting a partially specified block in the selected block design file;

specifying an implementation of the selected partially specified block using a design file editor.

10. The method of claim 9, wherein the design file editor comprises a text editor.

11. The method of claim 9, wherein the design file editor comprises a schematic editor.

12. The method of claim 1, further comprising generating a hierarchy information file relating the first graphic design file and the block design files, thereby facilitating incorporation of the modifications.

13. The method of claim 12, further comprising using the hierarchy information file to determine whether a first modification to one of the first graphic design file and the block design files requires modification to any other of the first graphic design file and the block design files.

14. The method of claim 1, wherein one of the imported fully specified or partially specified block design files correspond to a design file template.

15. At least one computer readable medium containing program instructions for designing a circuit using graphic editor software, said at least one computer readable medium comprising:

computer readable code for generating a first graphic design file, created in a graphical user interface associated with the graphic editor software, by importing one or more fully specified or partially specified block design files in one of a plurality of formats; and

computer readable code for generating a first block diagram, the first block diagram comprising a plurality of blocks and a plurality of conduits interconnecting the blocks, wherein at least one of the blocks corresponds to at least one of the fully specified or partially specified block design files,

wherein modifications to any of the first graphic design file and the block design files are incorporated into each other under software control.

16. The at least one computer readable medium of claim 15, wherein computer readable code for generating the first graphic design file further comprises:

computer readable code for determining the blocks with unassigned I/O in the first block diagram;

computer readable code for assigning I/O to each of the block with unassigned I/O in the first block diagram;

computer readable code for assigning at least one signal name for each conduit in the first block diagram; and

computer readable code for determining correspondence between the I/O and the at least one signal name.

17. The at least one computer readable medium of claim 15, wherein computer readable code for generating the first graphic design file further comprises:

computer readable code for assigning external I/O to the first block diagram.

18. The at least one computer readable medium of claim 17, wherein the external I/O corresponds to a pin out of a chip.

19. The at least one computer readable medium of claim 17, wherein the external I/O is a connection to a second block diagram with a second hierarchy level different from a first hierarchy level of the first block diagram.

20. The at least one computer readable medium of claim 15, wherein the plurality of formats includes at least one text format.

21. The at least one computer readable medium of claim 15, wherein selected ones of the conduits each represent a plurality of bi-directional signal paths.

22. The at least one computer readable medium of claim 15, wherein said one or more fully specified or partially specified block design files respectively specify a full implementation or a partial implementation of one or more blocks.

23. The at least one computer readable medium of claim 15, wherein computer readable code for generating the block design file further comprises:

computer readable code for selecting one block design file from the imported partially specified block design files;

computer readable code for selecting a partially specified block in the selected block design file;

computer readable code for specifying an implementation of the selected partially specified block using a design file editor.

24. The at least one computer readable medium of claim 23, wherein the design file editor comprises a text editor.

25. The at least one computer readable medium of claim 23, wherein the design file editor comprises a schematic editor.

26. The at least one computer readable medium of claim 15, further comprising computer readable code for generating a hierarchy information file relating the first graphic design file and the block design files, thereby facilitating incorporation of the modifications.

27. The at least one computer readable medium of claim 26, further comprising using the hierarchy information file to determine whether a first modification to one of the first graphic design file and the block design files requires modification to any other of the first graphic design file and the block design files.

28. The at least one computer readable medium of claim 15, wherein one of the imported fully specified or partially specified block design files correspond to a design file template.

29. A circuit designed by a method comprising:

generating a first graphic design file, created in a graphical user interface associated with a graphic editor software, by importing one or more fully specified or partially specified block design files in one of a plurality of formats; and

generating a first block diagram, the first block diagram comprising a plurality of blocks and a plurality of conduits interconnecting the blocks, wherein at least one of the blocks corresponds to at least one of the fully specified or partially specified block design files,

wherein modifications to any of the first graphic design file and the block design files are incorporated into each other under software control.