Method and apparatus for controlling anti-phase domains in semiconductor structures and devices

• US 6,589,856 B2
• Filed: 08/06/2001
• Issued: 07/08/2003
• Est. Priority Date: 08/06/2001
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Curless, Jay A.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/921,905
• Publication Number:
  US 20030027408A1
• Time in Patent Office: 701 Days
• Field of Search: 438/479, 438/517
• US Class Current: 438/479
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 25/18 characterised by the substrate
• CPC Class Codes: C30B 29/22 Complex oxides
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/31691 with perovskite structure

Abstract

High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer has a lattice registry to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The layers of the semiconductor structure may be manufactured in such a way as to control the formation of anti-phase domains so that the structure may operate without the deleterious effects associated with such defects. Such manufacture may include heat treating the substrate to essentially or completely eliminate single steps (anti-phase domains) by forming double steps that can transfer to the oxide interface layer and suppress the formation of anti-phase domains by forming double step therein, in preference to single steps.

Claims

1. A method for fabricating a semiconductor structure capable of controlling antiphase domains in the semiconductor structure, the method comprising:

providing a monocrystalline silicon substrate;

depositing a monocrystalline perovskite oxide film overlying the monocrystalline silicon substrate, the film having a thickness less than a thickness of the material that would result in strain-induced defects;

forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate;

epitaxially forming a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide film; and

suppressing the formation of anti-phase domains during fabrication of the semiconductor structure.

2. The method according to claim 1, wherein the anti-phase domains are suppressed by heat treating the monocrystalline silicon substrate to form double steps from single steps, thereby avoiding anti-phase domains in the semiconductor structure.

3. The method according to claim 2, wherein the heat treating is performed at a temperature greater than approximately 1000°

C.

4. The method according to claim 3, wherein the anti-phase domains are suppressed by transferring the double steps formed in the substrate to the oxide interface layer.

5. The method according to claim 1, wherein the anti-phase domains are suppressed by:

pre-exposing the amorphous oxide interface layer to a monoatomic layer of the monocrystalline compound semiconductor for an amount of time adequate to ensure uniform coverage of the amorphous oxide interface layer; and

using a tilted substrate to ensure formation of a preponderence of double steps compared to single steps.

6. A method for fabricating a semiconductor structure capable of controlling anti-phase domains in the semiconductor structure, the method comprising:

providing a monocrystalline silicon substrate;

depositing a monocrystalline perovskite oxide film overlying the monocrystalline silicon substrate, the film having a thickness less than a thickness of the material that would result in strain-induced defects;

forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate;

epitaxially forming a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide film; and

inducing double step formation during the fabrication of the semiconductor structure to reduce single steps, thereby controlling anti-phase domains in the semiconductor structure.

7. The method according to claim 6, wherein the double step formation is induced by heat treating the monocrystalline silicon substrate before the perovskite oxide film is deposited.

8. The method according to claim 6, wherein a transference of the double steps to the surface of the perovskite oxide film occurs during the deposition of the pervoskite oxide film.