Semiconductor structure for use with high-frequency signals

• US 6,590,236 B1
• Filed: 07/24/2000
• Issued: 07/08/2003
• Est. Priority Date: 07/24/2000
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: El-Zein, Nada, Ramdani, Jamal, Droopad, Ravindranath, Eisenbeiser, Kurt
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R.
• Application Number:
  US09/624,296
• Time in Patent Office: 1,079 Days
• Field of Search: 257/2, 257/78, 257/200, 257/201, 257/275, 257/607, 257/609, 257/613, 257/615, 257/616, 257/916, 257/917, 438/190, 438/407, 438/520, 438/528, 438/548, 438/752, 438/900, 438/918, 438/933
• US Class Current: 257/201
• CPC Class Codes: C30B 25/18 characterised by the substrate
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: Y10S 438/90 Bulk effect device making
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. These semiconductor materials have applications involving communications with high frequency signals including intelligent transportation systems such as automobile radar systems, smart cruise control systems, collision avoidance systems, and automotive navigation systems; and electronic payment systems that use microwave or RF signals such as electronic toll payment for various transportation systems including train fares, and toll roads, parking structures, and toll bridges for automobiles.

Claims

1. A monolithically integrated communications circuit structure comprising:

a monocrystalline silicon substrate;

a first monocrystalline oxide layer comprising a first material formed overlying a first portion of the substrate;

a first amorphous layer underlying the first monocrystalline oxide layer;

a first layer of monocrystalline compound semiconductor material of first type formed overlying the first oxide layer;

a second monocrystalline oxide layer comprising a second material different than the first material formed overlying a second portion of the substrate;

a second amorphous layer underlying the second monocrystalline oxide layer; and

a second layer of monocrystalline compound semiconductor material of second type different than the first type formed overlying the second oxide layer.

2. The structure of claim 1 wherein the first material comprises an alkaline earth metal titanate.

3. The structure of claim 2 wherein the first material comprises (Sr,Ba)TiO₃.

4. The structure of claim 2 wherein the first layer of monocrystalline compound semiconductor material comprises a material selected from the group consisting of GaAs, AlGaAs, ZnSe, and ZnSeS.

5. The structure of claim 4 further comprising a digital MOS circuit formed at least partially in the silicon substrate and a circuit capable of operation at a nominal frequency greater than about 2 GHz formed at least partially in the first layer of monocrystalline compound semiconductor material.

6. The structure of claim 2 further comprising a first template layer formed on the first portion.

7. The structure of claim 6 wherein the first template layer comprises 1-10 monolayers of material selected from the group consisting of Zn—

O, Sr—

S, Ti—

As, Sr—

O—

As, Sr—

Ga—

O, and Sr—

Al—

O.

8. The structure of claim 1 wherein the second material comprises an oxide selected from the group consisting of alkaline earth metal zirconates and alkaline earth metal hafnates.

9. The structure of claim 8 wherein the second layer of monocrystalline compound semiconductor material comprises a material selected from the group consisting of InP, AlInAs, AlGaInAsP, and InGaAs.

10. The structure of claim 9 further comprising a digital MOS circuit formed at least partially in the silicon substrate and a second circuit capable of operation at a nominal frequency greater than about 70 GHz formed at least partially in the second layer of monocrystalline compound semiconductor material.

11. The structure of claim 10 wherein the second circuit comprises a radar transceiver circuit.

12. The structure of claim 9 further comprising a second template layer formed on the second portion.

13. The structure of claim 12 wherein the second template layer comprises 1-10 monolayers of material having a composition M—

N or M—

O—

N wherein M is selected from the group consisting of Zr, Hf, Sr, and Ba and N is selected from the group consisting of As, P, Ga, Al, and In.

14. The structure of claim 1 further comprising:

a digital circuit formed in at least partially in the silicon substrate;

an oscillator circuit formed at least partially in the first layer of monocrystalline compound semiconductor material;

a transceiver circuit formed at least partially in the second layer of monocrystalline compound semiconductor material; and

an interconnection coupling together the digital circuit, the oscillator circuit, and the transceiver circuit.

15. A monolithically integrated communications circuit structure comprising:

a monocrystalline silicon substrate;

a first amorphous oxide layer comprising a first material formed overlying a first portion of the substrate;

a first layer of monocrystalline compound semiconductor material of first type formed overlying the first amorphous oxide layer;

a second amorphous oxide layer comprising a second material different than the first material formed overlying a second portion of the substrate; and

a second layer of monocrystalline compound semiconductor material of second type different than the first type formed overlying the second amorphous oxide layer.

16. A monolithically integrated circuit comprising:

a monocrystalline silicon substrate;

a monocrystalline oxide layer epitaxially grown overlying the silicon substrate;

an amorphous layer underlying the monocrystalline oxide layer;

a monocrystalline compound semiconductor layer epitaxially grown overlying the monocrystalline oxide layer;

a CMOS digital circuit formed at least partially in the silicon substrate; and

a communication circuit configured to operate at a frequency greater than 2 GHz formed at least partially in the compound semiconductor layer.

17. The circuit of claim 16 wherein the monocrystalline compound semiconductor layer comprises GaAs.

18. The circuit of claim 17 wherein the communications circuit comprises a signal modulator, an oscillator, and a transceiver.

19. The circuit of claim 18 wherein the oscillator is configured to operate at a frequency of 38 GHz.

20. The circuit of claim 18 wherein the transceiver is configured to operate at a frequency of 76-77 GHz.

21. The circuit of claim 17 wherein the communications circuit comprises a HEMT structure.

22. The circuit of claim 17 wherein the oxide layer comprises an alkali earth metal titanate.

23. The circuit of claim 22 wherein the oxide layer comprises (Ba,Sr)TiO₃.

24. The circuit of claim 16 wherein the monocrystalline compound semiconductor layer comprises InP.

25. The circuit of claim 24 wherein the oxide layer comprises a material selected from the group consisting of alkali earth metal hafnates and alkali earth metal zirconates.

26. The circuit of claim 24 wherein the communications circuit comprises a radar transceiver.

27. The circuit of claim 26 wherein the radar transceiver is configured to operate at a frequency of 76-77 GHz.

28. The circuit of claim 16 further comprising an interconnection coupling the CMOS digital circuit and the communications circuit.

29. A monolithically integrated circuit comprising:

a monocrystalline silicon substrate;

a monocrystalline oxide layer epitaxially grown overlying the silicon substrate;

an amorphous silicon oxide layer underlying the monocrystalline oxide layer;

a monocrystalline compound semiconductor layer comprising GaAs epitaxially grown overlying the monocrystalline oxide layer;

a transponder circuit configured to operate at a frequency greater than 5 GHz formed at least partially in the monocrystalline compound semiconductor layer; and

a CMOS digital control circuit formed at least partially in the silicon substrate and coupled to the transponder circuit.

30. The circuit of claim 29 wherein the digital control circuit comprises a memory and the transponder circuit is configured to receive information from an external chip and to transfer that information to the memory.

31. The circuit of claim 29 wherein the monocrystalline oxide layer comprises an alkaline earth metal titanate.

32. A monolithically integrated communications circuit structure comprising:

a monocrystalline silicon substrate;

a first oxide layer comprising a first material of (Sr,Ba)TiO₃ formed overlying a first portion of the substrate;

a first layer of monocrystalline compound semiconductor material of first type formed overlying the first oxide layer;

a second oxide layer comprising a second material different than the first material formed overlying a second portion of the substrate; and

a second layer of monocrystalline compound semiconductor material of second type different than the first type formed overlying the second oxide layer.

33. A monolithically integrated communications circuit structure comprising:

a monocrystalline silicon substrate;

a first oxide layer comprising a first material formed overlying a first portion of the substrate;

a first template layer formed on the first portion;

a first layer of monocrystalline compound semiconductor material of first type formed overlying the first oxide layer;

a second oxide layer comprising a second material different than the first material formed overlying a second portion of the substrate; and

a second layer of monocrystalline compound semiconductor material of second type different than the first type formed overlying the second oxide layer.

34. The structure of claim 33 wherein the first material comprises an alkaline earth metal titanate.

35. The structure of claim 33 wherein the first template layer comprises 1-10 monolayers of material selected from the group consisting of Zn—

O, Sr—

S, Ti—

As, Sr—

O—

As, Sr—

Ga—

O, and Sr—

Al—

O.

36. The structure of claim 33 wherein the second material comprises an oxide selected from the group consisting of alkaline earth metal zirconates and alkaline earth metal hafnates.

37. The structure of claim 36 wherein the second layer of monocrystalline compound semiconductor material comprises a material selected from the group consisting of InP, AlInAs, AlGaInAsP, and InGaAs.

38. The structure of claim 37 further comprising a digital MOS circuit formed at least partially in the silicon substrate and a second circuit capable of operation at a nominal frequency greater than about 70 GHz formed at least partially in the second layer of monocrystalline compound semiconductor material.

39. The structure of claim 38 wherein the second circuit comprises a radar transceiver circuit.

40. The structure of claim 38 further comprising a second template layer formed on the second portion.

41. The structure of claim 40 wherein the second template layer comprises 1-10 monolayers of material having a composition M—

N or M—

O—

N wherein M is selected from the group consisting of Zr, Hf, Sr, and Ba and N is selected from the group consisting of As, P, Ga, Al, and In.

42. The structure of claim 33 further comprising:

a digital circuit formed in at least partially in the silicon substrate;

an oscillator circuit formed at least partially in the first layer of monocrystalline compound semiconductor material;

a transceiver circuit formed at least partially in the second layer of monocrystalline compound semiconductor material; and

an interconnection coupling together the digital circuit, the oscillator circuit, and the transceiver circuit.

43. The structure of claim 33 wherein the first oxide layer comprises a first monocrystalline oxide layer and the second oxide layer comprises a second monocrystalline oxide layer.

44. The structure of claim 43 further comprising a first amorphous layer underlying the first oxide layer and a second amorphous layer underlying the second oxide layer.

45. The structure of claim 33 wherein the first oxide layer comprises a first amorphous oxide layer and the second oxide layer comprises a second amorphous oxide layer.

46. A monolithically integrated circuit comprising:

a monocrystalline silicon substrate;

an oxide layer epitaxially grown overlying the silicon substrate;

a monocrystalline compound semiconductor layer epitaxially grown overlying the oxide layer;

a CMOS digital circuit formed at least partially in the silicon substrate;

a communication circuit configured to operate at a frequency greater than 2 GHz formed at least partially in the compound semiconductor layer; and

the communications circuit comprising a signal modulator, an oscillator, and a transceiver, the oscillator being configured to operate at a frequency of 38 GHz.

47. The circuit of claim 46 wherein the monocrystalline compound semiconductor layer comprises GaAs.

48. The circuit of claim 46 wherein the transceiver is configured to operate at a frequency of 76-77 GHz.

49. A monolithically integrated circuit comprising:

a monocrystalline silicon substrate;

an oxide layer epitaxially grown overlying the silicon substrate;

a monocrystalline compound semiconductor layer epitaxially grown overlying the oxide layer;

a CMOS digital circuit formed at least partially in the silicon substrate;

a communication circuit configured to operate at a frequency greater than 2 GHz formed at least partially in the compound semiconductor layer; and

the communications circuit comprising a signal modulator, an oscillator, and a transceiver, the transceiver being configured to operate at a frequency of 76-77 GHz.

50. The circuit of claim 49 wherein the monocrystalline compound semiconductor layer comprises GaAs.

51. The circuit of claim 49 wherein the oscillator is configured to operate at a frequency of 38 GHz.

52. A monolithically integrated circuit comprising:

a monocrystalline silicon substrate;

an oxide layer epitaxially grown overlying the silicon substrate;

a monocrystalline compound semiconductor layer epitaxially grown overlying the oxide layer;

a CMOS digital circuit formed at least partially in the silicon substrate;

a communication circuit configured to operate at a frequency greater than 2 GHz formed at least partially in the compound semiconductor layer; and

the communications circuit comprising a HEMT structure.

53. The circuit of claim 52 wherein the monocrystalline compound semiconductor layer comprises GaAs.

54. A monolithically integrated circuit comprising:

a monocrystalline silicon substrate;

an oxide layer epitaxially grown overlying the silicon substrate;

a monocrystalline compound semiconductor layer of InP epitaxially grown overlying the oxide layer;

a CMOS digital circuit formed at least partially in the silicon substrate; and

a communication circuit configured to operate at a frequency greater than 2 GHz formed at least partially in the compound semiconductor layer.

55. The circuit of claim 54 wherein the oxide layer comprises (Ba,Sr)TiO₃.

56. The circuit of claim 54 wherein the oxide layer comprises a material selected from the group consisting of alkaline earth metal hafnates and alkaline earth metal zirconates.

57. The circuit of claim 54 wherein the communications circuit comprises a radar transceiver.

58. The circuit of claim 57 wherein the radar transceiver is configured to operate at a frequency of 76-77 GHz.

59. The circuit of claim 54, further comprising an interconnection coupling the CMOS digital circuit and the communications circuit.