ESD protection configuration for signal inputs and outputs in semiconductor devices with substrate isolation

• US 6,590,263 B2
• Filed: 03/18/2002
• Issued: 07/08/2003
• Est. Priority Date: 09/16/1999
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Gossner, Harald
• Primary Examiner(s): Fahmy, Jr., Wael
• Assistant Examiner(s): Farahani, Dana
• Application Number:
  US10/100,238
• Publication Number:
  US 20020121668A1
• Time in Patent Office: 477 Days
• Field of Search: 257/487, 257/355, 257/356, 257/357, 257/358, 257/359, 257/360, 257/365, 257/173, 257/174
• US Class Current: 257/355
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12035 Zener diode
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

In the ESD protection configuration, in addition to the existing protection configurations, at each supply pad of the supply bus, an ESD diode is also inserted between the power bus with the potential VSSP and the supply bus with the supply potential VDDP. This ESD diode closes the protection path for negative loads between the substrate potential VSSB and the potential VSSP during an ESD stress and limits the voltage difference occurring between the two corresponding buses (the substrate bus and the power bus) to the terminal voltage of the breakdown diode plus the forward voltage of the ESD diode. The ESD diode between the power bus and the supply bus is intended to be operated only in the forward direction. This requires the breakdown voltage of the ESD diode to be significantly above the breakdown voltage of the breakdown diode of the supply bus.

Claims

1. An ESD protection configuration for semiconductor devices having I/O pads and substrate isolation, comprising:

a semiconductor substrate;

a substrate bus connected to said semiconductor substrate for applying a substrate potential to said semiconductor substrate;

a semiconductor diffusion zone formed in said semiconductor substrate;

a power bus connected to said semiconductor diffusion zone for applying a power potential to said semiconductor diffusion zone;

a parasitic diode connected between said substrate bus and said power bus, said parasitic diode acting in an event of a positive voltage load on the I/O pads;

a supply bus for feeding a supply potential to the semiconductor devices; and

a breakdown diode connected between said substrate bus and said supply bus, said breakdown diode becoming forward-biased

in an event of a negative voltage load on the I/O pads, said breakdown diode having a breakdown voltage;

an additional ESD diode provided between said power bus and said supply bus;

said additional ESD diode becoming forward-biased in the event of the negative voltage load;

said additional ESD diode having a breakdown voltage being higher than said breakdown voltage of said breakdown diode.

2. The ESD protection configuration according to claim 1, wherein said semiconductor device includes a driver.

3. The ESD protection configuration according to claim 2, wherein said driver has an NMOS transistor.

4. The ESD protection configuration according to claim 3, wherein:

said NMOS transistor has a source; and

said parasitic diode is connected between said source of said NMOS transistor and said substrate bus.

5. The ESD protection configuration according to claim 1, wherein said breakdown diode is connected directly between said substrate bus and said supply bus, and said additional ESD diode is connected directly between said power bus and said supply bus.