Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

• US 6,590,415 B2
• Filed: 04/23/2001
• Issued: 07/08/2003
• Est. Priority Date: 10/09/1997
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Agrawal, Om P., Nguyen, Bai, Sharpe-Geisler, Bradley A., Chang, Herman M., Tran, Giap H.
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US09/841,209
• Publication Number:
  US 20020196809A1
• Time in Patent Office: 806 Days
• Field of Search: 326/40, 326/38, 326/39, 326/41, 326/46, 326/47
• US Class Current: 326/38
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE'"'"'s) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE'"'"'s) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions.

Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE'"'"'s may be synthetically combined to efficiently define 4:1 DyMUX'"'"'s with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB'"'"'s may be synthetically combined to efficiently define 8:1 DyMUX'"'"'s with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB'"'"'s may be synthetically combined to efficiently define higher order, N:1 DyMUX'"'"'s.

Claims

1. A programmed field programmable gate array (FPGA) wherein said FPGA, in an unprogrammed state thereof is characterized as having a plurality of variably granulatable building elements provided in respective building block regions of the FPGA such that the building elements can be folded-together during configuration of the unprogrammed FPGA to thereby define differently-sized logic-implementing units and wherein said unprogrammed FPGA further has Configurable Sequential Elements (CSE'"'"'s) associated with the building blocks for storing and outputting respective result signals to adjacent interconnect lines, wherein each CSE includes a plurality of registers where at least two of the registers of a given CSE can be each configurably coupled to receive and store a respective logic result signal produced by one or a folded-together combination of said building elements, and wherein a building block of said programmed FPGA comprises:

(a) input acquiring means for selectively acquiring an input signal from adjacent interconnect lines;

(b) a configured first forwarding means for forwarding the acquired input signal to a corresponding CSE;

(c) a return mechanism for returning the forwarded input signal to at least one building element of the building block for processing by the at least one building element; and

(d) a configured second forwarding means for forwarding the processed signal to the corresponding CSE for output by the corresponding CSE to an adjacent interconnect line.

2. The programmed FPGA of claim 1 wherein:

(b.1) the a configured first forwarding means includes a dynamic multiplexer for dynamically selecting the acquired input signal that is sent to the corresponding CSE.

3. The programmed FPGA of claim 2 wherein:

(b.2) a plurality of building blocks of said programmed FPGA are configured to respectively and dynamically select respective ones of acquired input signals from dynamically selectable buses for forwarding to corresponding CSEs.

4. A field programmable gate array (FPGA) having a plurality of variably granulatable building elements provided in respective variable grain blocks (VGB'"'"'s) of the FPGA such that the building elements can be folded-together during configuration of the FPGA to thereby define differently-sized logic-implementing units and wherein said FPGA further has output means for outputting respective result signals of VGB'"'"'s to adjacent interconnect lines, wherein:

(a) at least two of said VGB'"'"'s can be each configured to implement at least an N-to-one (N;

1) dynamic multiplexer, where N is an integer of value 4 or greater; and

(b) the FPGA further has for at least said two of the VGB'"'"'s, a shared dynamic multiplexer that can be configured to dynamically select between outputs of the N;

1 dynamic multiplexers of said at least two VGB'"'"'s, thereby providing a dynamic multiplexing capability of at least two-times N.

5. The FPGA of claim 4 wherein N is at least eight.

6. The FPGA of claim 4 wherein:

(b.1) the shared dynamic multiplexer can be configured to dynamically select between outputs of the N;

1 dynamic multiplexers of at least four VGB'"'"'s, thereby providing a dynamic multiplexing capability of at least four-times N.

7. A field programmable gate array (FPGA) comprising:

(a) a plurality of variably granulatable building elements provided in respective variable grain blocks (VGB'"'"'s) of the FPGA such that the building elements can be folded-together during configuration of the FPGA to thereby define in each of the VGB'"'"'s, programmably-sized dynamic multiplexing units each having a respective number of dynamically multiplexable inputs corresponding to the programmably-defined size of the respective dynamic multiplexing unit; and

(b) at least one, shared dynamic mulitiplexer that is shareable by plural ones of the VGB'"'"'s at least for implementing by combination with the programmably-sized dynamic multiplexing units of the sharing VGB'"'"'s, an N;

1 dynamic multiplexer having a number of dynamically multiplexable inputs greater than the number of dynamically multiplexable inputs supportable by each of the programmably-sized dynamic multiplexing units which can be implemented in the plural VGB'"'"'s that share said shared dynamic mulitiplexer.

8. The FPGA of claim 7 wherein the number of dynamically multiplexable inputs of said N:

1 dynamic multiplexer is at least twice that of the dynamically multiplexable inputs supportable by each of the programmably-sized dynamic multiplexing units which can be implemented in the plural VGB'"'"'s that share said shared dynamic mulitiplexer.

9. The FPGA of claim 8 wherein each of the programmably-sized dynamic multiplexing units in the respective VGB'"'"'s can implement at least a 8:

1 dynamic multiplexer so that said N;

1 dynamic multiplexer can thereby provide at least a 16;

1 dynamic multiplexing function.

10. The FPGA of claim 8 wherein each of the programmably-sized dynamic multiplexing units in the respective VGB'"'"'s can implement at least a 13:

1 dynamic multiplexer so that said N;

1 dynamic multiplexer can thereby provide at least a 26;

1 dynamic multiplexing function.

11. The FPGA of claim 10 wherein the number of dynamically multiplexable inputs of said N:

1 dynamic multiplexer is at least four times that of the dynamically multiplexable inputs supportable by each of the programmably-sized dynamic multiplexing units which can be implemented in the plural VGB'"'"'s that share said shared dynamic mulitiplexer, so that said N;

1 dynamic multiplexer can thereby provide at least a 52;

1 dynamic multiplexing function.

12. The FPGA of claim 7 wherein the number of dynamically multiplexable inputs of said N:

1 dynamic multiplexer is at least four times that of the dynamically multiplexable inputs supportable by each of the programmably-sized dynamic multiplexing units which can be implemented in the plural VGB'"'"'s that share said shared dynamic mulitiplexer.

13. A method of using a field programmable gate array (FPGA) to implement a dynamic multiplexing function,

(0.1) where the FPGA has a plurality of variably granulatable building elements provided in respective variable grain blocks (VGB'"'"'s) of the FPGA such that the building elements can be folded-together during configuration of the FPGA to thereby define in each of the VGB'"'"'s, programmably-sized dynamic multiplexing units each having a respective number of dynamically multiplexable inputs corresponding to the programmably-defined size of the respective dynamic multiplexing unit;

and

(0.2) where the FPGA further has at least one, shared dynamic mulitiplexer that is shareable by plural ones of the VGB'"'"'s at least for implementing by combination with the programmably-sized dynamic multiplexing units of the sharing VGB'"'"'s, an N;

1 dynamic multiplexer having a number of dynamically multiplexable inputs greater than the number of dynamically multiplexable inputs supportable by each of the programmably-sized dynamic multiplexing units which can be implemented in the plural VGB'"'"'s that share said shared dynamic mulitiplexer;

said method comprising;

(a) configuring at least two VGB'"'"'s to implement respective and same sized dynamic multiplexing units; and

(b) configuring a shared dynamic mulitiplexer of the at least two VGB'"'"'s to implement said N;

1 dynamic multiplexer.