Method and system for run-time logic verification of operations in digital systems

• US 6,590,929 B1
• Filed: 06/08/1999
• Issued: 07/08/2003
• Est. Priority Date: 06/08/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Williams, Derek Edward
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/328,300
• Time in Patent Office: 1,491 Days
• Field of Search: 375/224, 375/240.27, 375/265, 714/704, 714/705, 714/746, 714/801, 714/798, 714/804, 714/733, 714/734, 714/728, 714/739, 714/738, 714/769, 714/33
• US Class Current: 375/224
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test

Abstract

A system for controllable run-time verification of operations in a logic structure of a digital system. The system comprises a controllable bit stream generator which produces a controlled bit stream output. The controlled bit stream output corresponds to a bit sequence which instantiates a verification of operations within the logic structure. The system also comprises means for coupling the controlled bit stream output to the logic structure to verify the operations of the logic structure.

Claims

1. A system for controllable run-time verification of operations in a logic structure of a digital system, said system comprising:

a controllable bit stream generator having means for producing a controlled bit stream output, said controlled bit stream output corresponding to a bit sequence which instantiates a verification of operations within said logic structure;

means for coupling said controlled bit stream output to said logic structure; and

means for verifying said operations of said logic structure by simulating an error input to said logic structure, wherein said error input is generated by said controlled bit stream output.

2. The system of claim 1, wherein:

said logic structure includes;

a virtual 2-read, 1-write port array;

a parity check logic coupled to said array for checking an error in a data read from said array; and

an error correction sequencer coupled to said parity check logic which corrects said error when it is found; and

said verifying means includes;

an OR gate with a dual input; and

means for connecting said controlled bit stream and an output of said parity check logic to said dual input of said OR gate respectively and logically ORing an error signal of parity check modules within said controlled bit stream output.

3. The system of claim 2, said verifying means includes means for instantiating a verification process by injecting a false error into said error correction sequencer.

4. The system of claim 3, said instantiating means includes means for randomly sending a signal via said controlled bit stream output which displays a similar characteristic as a corrupted data from said array.

5. A system for controllable run-time verification of operations in a logic structure of a digital system, said system comprising:

a controllable bit stream generator having means for producing a controlled bit stream output, said controlled bit stream output corresponding to a bit sequence which instantiates a verification of operations within said logic structure, wherein said controllable bit stream generator comprises;

means for generating a pseudo-random bit sequence;

a variable probability conditioner coupled to said generating means which accepts said pseudo-random bit sequence and outputs said controlled bit stream output; and

register means coupled to said variable probability conditioner, said register means for sending a control signal to said variable probability conditioner, wherein said control signal operates on said pseudo-random bit sequence to produce said corresponding controlled output;

means for coupling said controlled bit stream output to said logic structure; and

means for verifying said operations of said logic structure utilizing said controlled bit stream output.

6. The system of claim 5, wherein said generating means is a Linear Feedback Shift Register (LFSR) and said variable probability conditioner is a controllable LFSR conditioner further comprising:

means for transmitting said pseudo-random bit sequence said LFSR to said controllable LFSR conditioner;

means for selecting an output sequence of said controlled bit stream output based on a predetermined and controllable percentage, said percentage corresponding to a pre-selected percentage of time a bit from said output sequence should be active; and

means for outputting said output sequence.

7. The system of claim 6, wherein said controllable LFSR conditioner includes a pattern detection logic and a multiplexor (MUX), said selecting means further includes:

means for creating a plurality of random bit sources with distinct probabilities for the occurrence of an active value said means utilizing said pattern detection logic;

means for transmitting said plurality of random bit sources to said MUX simultaneously with said control signal from said register; and

means for combining said control signal with said random bit sources to create said output sequence.

8. The system of claim 7, wherein said pattern detection logic comprises:

a comparator for comparing said pseudo-random bit sequences with a predetermined set of desired patterns;

a logical OR gate coupled to said comparator to filter through said desired patterns; and

means for recognizing said desired patterns utilizing said comparator.

9. The system of claim 7, wherein said register means is coupled to said MUX.

10. The system of claim 6, wherein said pseudo-random bit sequence is a sub-set of a larger pseudo-random bit sequence of said LFSR.

11. The system of claim 6, wherein said register means includes a number of latches which provide control signals to said controllable LFSR conditioner, wherein further, said number of latches contain control information loaded in one of a plurality of ways including software register loading and scan-chain initialization, and said control signals are utilized by said controllable LFSR conditioner to select said percentage of time said bit of said output sequence is active.

12. A system for controllable run-time verification of operations in a logic structure of a digital system, said system comprising:

a controllable bit stream generator having means for producing a controlled bit stream output, said controlled bit stream output corresponding to a bit sequence which instantiates a verification of operations within said logic structure;

means for coupling said controlled bit stream output to said logic structure, wherein said logic structure includes a data array coupled via a plurality of logic gates to an error correcting code (ECC) encoder which detects and corrects a single bit error in said data; and

means for verifying said operations of said logic structure utilizing said controlled bit stream output, said verifying means includes;

means for instantiating a generation of said controlled bit stream output wherein a sequence of bits represents said data; and

means for sending said controlled bit stream output to said plurality of logic gates.

13. A system for controllable run-time verification of operations of a unique path through a logic design error correction sequencer, said system comprising:

means for deliberately simulating an error within said error correction sequencer, wherein said simulating means includes a controllable bit stream generator and further comprises means for coupling a controlled bit stream output of said controllable bit stream generator to an input of said error correction sequencer, wherein said controlled bit stream output includes said error; and

means for monitoring a response by said error correction sequencer to said error.

14. The system of claim 13, wherein said simulating means includes means for controlling said controlled bit stream output to yield a desired failure rate of said error correction sequencer.

15. A system for controllable run-time verification of operations of a unique path through a logic design error correction sequencer, said system comprising:

means for simulating an error within said error correction sequencer, wherein said simulating means includes a controllable bit stream generator and further comprises means for coupling a controlled bit stream output of said controllable bit stream generator to an input of said error correction sequencer, wherein said controlled bit stream output includes an error, and wherein said controllable bit stream generator includes;

means for generating a pseudo-random bit sequence;

a variable probability conditioner coupled to said generating means which accepts said pseudo-random bit sequence and outputs a corresponding controlled bit stream output; and

register means coupled to said variable probability conditioner, said register means for sending a control signal to said variable probability conditioner wherein said control signal operates on said pseudo-random bit sequence to produce said corresponding controlled bit stream output; and

means for monitoring a response by said error correction sequencer to said error.

16. A system for controllable run-time verification of operations of a unique path through a logic design error correction sequencer, said system comprising:

a detection logic;

means for simulating an error within said error correction sequencer, said means for simulating including a controllable bit stream generator and means for coupling a controlled bit stream output of said controllable bit stream generator to an input of said error correction sequencer, wherein said controlled bit stream output includes said error; and

means for monitoring a response by said error correction sequencer to said error, wherein said monitoring means monitors a specific operating condition of a digital system and includes

means for sending an output signal from said detection logic upon an occurrence of said specific operating condition, said output signal being logically connected to said controlled bit stream output, wherein said error is simulated only upon said occurrence.

17. The system of claim 16, wherein said detection logic is located externally to said digital system.

18. A method for providing controllable run-time verification of operations in a logic structure of a digital system, said method comprising the steps of:

producing a controlled bit stream output via a controllable bit stream generator, said controlled bit stream output corresponding to a bit sequence which instantiates a verification of operations within said logic structure;

coupling said controlled bit stream output to said logic structure; and

verifying said operations of said logic structure by simulating an error input to said logic structure, wherein said error input is generated by said controlled bit stream output.

19. The method of claim 18, wherein said logic structure includes a virtual 2-read, 1-write port array, a parity check logic coupled to said array for checking an error in a data read from said array;

and an error correction sequencer coupled to said parity check logic which corrects said error when it is found, wherein further said verifying step includes the steps of connecting said controlled bit stream and an output of said parity check logic to a respective input of an OR gate and logically ORing an error signal of parity check modules within said controlled bit stream output.

20. The method of claim 19, said verifying step includes the step of instantiating a verification process by injecting a false error into said error correction sequencer.

21. The method of claim 20, said instantiating step further includes the step of randomly sending a signal via said controlled bit stream output which displays a similar characteristic as a corrupted data from said array.

22. A method for providing controllable run-time verification of operations in a logic structure of a digital system, said method comprising the steps of:

producing a controlled bit stream output via a controllable bit stream generator, said controlled bit stream output corresponding to a bit sequence which instantiates a verification of operations within said logic structure, wherein said producing step includes;

generating a pseudo-random bit sequence;

producing a corresponding controlled bit stream output from said pseudo-random bit sequence, said producing step utilizing a variable probability conditioner; and

sending a control signal to said variable probability conditioner, wherein said control signal operates on said pseudo-random bit sequence to produce said corresponding controlled bit stream output and said control signal originating from a register coupled to said variable probability conditioner;

coupling said controlled bit stream output to said logic structure; and

verifying said operations of said logic structure utilizing said controlled bit stream output.

23. The method of claim 22, wherein said generating step is completed by a Linear Feedback Shift Register (LFSR) and said variable probability conditioner is a controllable LFSR conditioner, said producing step further comprising the steps of:

transmitting said pseudo-random bit sequence from said LFSR to said controllable LFSR conditioner;

selecting an output sequence of said controlled bit stream output based on a predetermined and controllable percentage, said percentage corresponding to a pre-selected percentage of time a bit from said output sequence should be active; and

outputting said output sequence.

24. The method of claim 23, wherein said controllable LFSR conditioner includes a pattern detection logic and a multiplexor (MUX), said selecting step further includes the steps of:

creating a plurality of random bit sources with distinct probabilities for the occurrence of an active value said creating step utilizing said pattern detection logic;

transmitting said plurality of random bit sources to said MUX simultaneously with said control signal from said register; and

combining said control signal with said random bit sources to create said output sequence.

25. The method of claim 24, wherein said pattern detection logic comprises a comparator coupled to a logical OR gate and said creating step includes the steps of:

comparing said pseudo-random bit sequences with a predetermined set of desired patterns utilizing said comparator;

filtering through said desired patterns via said logical OR gate; and

recognizing said desired patterns utilizing said comparator.

26. The method of claim 24, wherein said register of said selecting step is coupled to said MUX.

27. The method of claim 23, wherein said transmitting step includes the step of selecting a subset of a larger pseudo-random bit sequence of said LFSR to utilize as said pseudo-random bit sequence.

28. The method of claim 23, wherein said register includes a number of latches, said selecting step further includes the step of providing control signals to said controllable LFSR conditioner, wherein further, said number of latches contain control information loaded in one of a plurality of ways including software register loading and scan-chain initialization, and said control signals are utilized by said controllable LFSR conditioner to select said percentage of time said bit of said output sequence is active.

29. A system for controllable run-time verification of operations in a logic structure of a digital system, said system comprising:

a controllable bit stream generator that produces a controlled bit stream output, said controlled bit stream output corresponding to a bit sequence which instantiates a verification of operations within said logic structure;

coupling logic to connect said controlled bit stream output to said logic structure;

error control logic that verifies said operations of said logic structure utilizing said controlled bit stream output; and

wherein said logic structure includes;

a virtual 2-read, 1-write port array;

a parity check logic coupled to said array for checking an error in a data read from said array;

an error correction sequencer coupled to said parity check logic which corrects said error when it is found; and

an OR gate with a dual input for logically ORing said controlled bit stream and an output of said parity check logic.