System and method for coarse/fine PLL adjustment

• US 6,591,091 B1
• Filed: 11/12/1999
• Issued: 07/08/2003
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Vorenkamp, Pieter, Bult, Klaas, Carr, Frank
• Primary Examiner(s): Nguyen, Lee
• Assistant Examiner(s): SOBUTKA, PHILIP
• Application Number:
  US09/438,688
• Time in Patent Office: 1,334 Days
• Field of Search: 455/179.1, 455/180.2, 455/180.6, 455/182.3, 455/183.1, 455/207, 455/208, 455/209, 455/189.1, 455/190.1, 455/192.1, 455/192.3, 455/313-6, 455/318, 455/323, 455/324, 455/337, 455/255, 455/258-60, 455/265, 455/84, 375/316, 375/347, 348/731, 348/735, 348/725, 348/726, 331/18
• US Class Current: 455/179.1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. A method of tuning a receiver that maintains a signal output from the receiver during the tuning process comprising:

selecting a channel to be tuned;

tuning the channel to approximately a desired first intermediate frequency by a first frequency source that is adjustable in coarse steps and having a wide bandwidth;

filtering the channel at the desired first intermediate frequency in a bandpass filter having passband that is sufficiently wide to pass the channel and a portion of another channel; and

tuning the channel at the first intermediate frequency to a second intermediate frequency by a second frequency source that is adjustable in fine steps and having a narrow bandwidth relative to the wide bandwidth of the first frequency source;

wherein the tuning steps are performed in accordance with the following equation;

2. The method of tuning a receiver that maintains a signal output from the receiver during the tuning process of claim 1 wherein the coarse step is 10 MHz.

3. The method of tuning a receiver that maintains a signal output from the receiver during the tuning process of claim 1 wherein the fine step is 100 KHz.

4. The method of tuning a receiver that maintains a signal output from the receiver during the tuning process of claim 1, wherein the portion of another channel is sufficiently wide to accommodate a frequency error in the channel caused by the coarse steps.

5. The method of tuning a receiver that maintains a signal output from the receiver during the tuning process of claim 4, wherein the portion of another channel is approximately 4 MHz.

6. A method of tuning a receiver that maintains a signal output from the receiver during the tuning process comprising:

selecting a channel to be tuned;

tuning the channel to approximately a desired first intermediate frequency by a frequency source that is adjustable in coarse steps;

bandpass filtering the channel at the desired first intermediate frequency so as to pass the channel and a portion of another channel;

tuning the channel at the first intermediate frequency to a second intermediate frequency by a frequency source that is adjustable in fine steps; and

tuning the channel at the second intermediate frequency to a third intermediate frequency by a direct synthesis frequency source having a divider circuit to produce an output frequency that is in a fixed relationship to the frequency source adjustable in fine steps.

7. The method of tuning a receiver that maintains a signal output from the receiver during the tuning process of claim 6, wherein the fixed relationship to the second frequency source adjustable in fine steps is a ratio of one-fourth.

8. The method of tuning a receiver that maintains a signal output from the receiver during the tuning process of claim 6, wherein the portion of another channel is sufficiently wide to accommodate a frequency error in the channel caused by the coarse steps.

9. The method of tuning a receiver that maintains a signal output from the receiver during the tuning process of claim 8, wherein the portion of another channel is approximately 4 MHz.

10. A method of tuning a receiver, comprising:

selecting a desired channel to be tuned;

tuning the desired channel to approximately a desired first intermediate frequency by using a first phase lock loop that is adjustable in coarse frequency steps and having a wide bandwidth;

filtering the desired channel at the desired first intermediate frequency in a bandpass filter having passband, the passband being wide enough to accommodate any frequency error of the desired channel relative to the desired first intermediate frequency that is caused by the coarse frequency steps; and

tuning the desired channel at the first intermediate frequency to a second intermediate frequency by a second phase lock loop that is adjustable in fine frequency steps and having a narrow bandwidth relative to the wide bandwidth of the first phase lock loop;

wherein the tuning steps are performed in accordance with the following equation;

11. The method of claim 10, wherein the coarse frequency steps are approximately 10 MHz.

12. The method of claim 10, wherein the fine frequency steps are approximately 100 kHz.

13. The method of claim 10, wherein the passband is sufficiently wide to accommodate up to 10 MHz of frequency error caused by the coarse frequency steps.