Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system

• US 6,591,348 B1
• Filed: 09/09/1999
• Issued: 07/08/2003
• Est. Priority Date: 09/09/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Tina Shui Wan, Deshpande, Sanjay Raghunath
• Primary Examiner(s): Hudspeth, David
• Assistant Examiner(s): TZENG, FRED
• Application Number:
  US09/392,833
• Time in Patent Office: 1,398 Days
• Field of Search: 711/141, 711/150, 711/152, 711/167, 711/168, 711/170, 712/28, 710/260, 714/800
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller'"'"'s master device buses. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency for commands by contributing one or more inputs into a determination of a coherency response for commands based on the types of commands and the phases of commands queued within the node controller. A response combination block logically combines, generates, and then transmits command status signals and command response signals associated with commands issued by master devices. The system is able to achieve the correct order of complete for transactions using these coherency inputs.

Claims

1. A method of maintaining cache coherency in a multiprocessor system, the method comprising the steps of:

receiving a transaction at a node controller during a local cycle;

broadcasting the transaction to master devices for a global snoop during a global cycle; and

contributing one or more inputs into a determination of a coherency response for the transaction.

2. The method of claim 1 further comprising:

providing the coherency response to a requester of the transaction in a primary response window of the transaction.

3. The method of claim 1 further comprising:

providing the coherency response to a requester of the transaction in a global response window of the transaction.

4. The method of claim 3 wherein the coherency response was previously stored in response to a determination that the transaction collides with another transaction.

5. The method of claim 3 wherein the coherency response is conditional with respect to a completion of a colliding transaction.

6. The method of claim 3 wherein the coherency response is unconditional with respect to a completion of a colliding transaction.

7. The method of claim 1 further comprising:

determining a contributed input for the coherency response according to one or more of the following conditions;

a phase of the transaction;

a transaction type of the transaction;

a transaction type of a snooped transaction; and

a bus protocol for communicating between the node controller and a requester of the transaction.

8. The method of claim 1 further comprising:

determining a contributed input for the coherency response according to a phase of the transaction.

9. The method of claim 8 wherein a phase of the transaction is determinable by the node controller as one of a plurality of phases.

10. The method of claim 9 wherein one phase in the plurality of phases of the transaction is defined as a time period consisting of a first cycle for the transaction within the node controller.

11. The method of claim 9 wherein one phase in the plurality of phases of the transaction is defined as a time period consisting of a second cycle for the transaction within the node controller to a last cycle for a primary response for the transaction.

12. The method of claim 9 wherein one phase in the plurality of phases of the transaction is defined as a time period consisting of a first cycle after a preceding phase until a last cycle before the node controller receives the transaction as a snooped transaction.

13. The method of claim 9 wherein one phase in the plurality of phases of the transaction is defined as a time period consisting of a first cycle in which the node controller receives the transaction as a snooped transaction.

14. The method of claim 9 wherein one phase in the plurality of phases of the transaction is defined as a time period consisting of a first cycle after a preceding phase until a global coherency response is received by the node controller for the transaction.

15. The method of claim 9 wherein one phase in the plurality of phases of the transaction is defined as a time period consisting of a first cycle after a preceding phase until the transaction completes.

16. The method of claim 9 wherein, if the transaction is a read transaction, one phase in the plurality of phases of the transaction is defined as a time period consisting of a first cycle after a preceding phase until a first cycle for transferring data to a requester of the transaction.

17. The method of claim 1 wherein the coherency response of the transaction is generated by a response combination block.

18. The method of claim 1 further comprising:

registering the received transaction in the node controller.

19. The method of claim 1 wherein the multiprocessor system comprises:

the node controller;

a plurality of master devices; and

a plurality of bidirectional master device buses, wherein each bidirectional master device bus connects one or more master devices within a node to a port of the node controller.

20. The method of claim 19 wherein the node controller comprises:

a plurality of master device ports, wherein each master device port connects to a master device bus;

a pair of address switch ports, wherein each address switch port connects to one of a pair of unidirectonal address switch buses, wherein one of the pair of address switch buses conveys an address from the node controller to the address switch and the other of the pair of address switch buses conveys an address from the address switch to the node controller; and

a plurality of memory subsystem ports, wherein each memory subsystem port connects to one of a plurality of bidirectional memory subsystem buses, wherein each bidirectional memory subsystem bus conveys data between the node controller and one of a plurality of memory subsystems.

21. A method of maintaining cache coherency in a multiprocessor system, the method comprising the steps of:

receiving a transaction at a node controller during a local cycle;

determining whether it is possible to predict a global coherence response;

predicting a global coherence response if it is possible to predict the global coherence response; and

providing the predicted global coherence response to a requester of the transaction in a primary response window for the transaction.

22. The method of claim 21, further comprising:

delivering a primary response that indicates postponement of a global coherence response to a requester of the transaction in a primary response window for the transaction if it is not possible to predict the global coherence response.

23. A multiprocessor system, comprising:

a node controller;

a plurality of master devices; and

a plurality of bidirectional master device buses, wherein each bidirectional master device bus connects one or more master devices within a node to a port of the node controller.

24. The multiprocessor of claim 23 wherein the node controller comprises:

a plurality of master device ports, wherein each master device port connects to a master device bus;

a pair of address switch ports, wherein each address switch port connects to one of a pair of unidirectional address switch buses, wherein one of the pair of address switch buses conveys an address from the node controller to the address switch and the other of the pair of address switch buses conveys an address from the address switch to the node controller; and

a plurality of memory subsystem ports, wherein each memory subsystem port connects to one of a plurality of bidirectional memory subsystem buses, wherein each bidirectional memory subsystem bus conveys data between the node controller and one of a plurality of memory subsystems.

25. A node controller, comprising:

a plurality of master device ports, wherein each master device port connects to a master device bus;

a pair of address switch ports, wherein each address switch port connects to one of a pair of unidirectional address switch buses, wherein one of the pair of address switch buses conveys an address from the node controller to the address switch and the other of the pair of address switch buses conveys an address from the address switch to the node controller; and

a plurality of memory subsystem ports, wherein each memory subsystem port connects to one of a plurality of bidirectional memory subsystem buses, wherein each bidirectional memory subsystem bus conveys data between the node controller and one of a plurality of memory subsystems.