Computer system with operating system functions distributed among plural microcontrollers for managing device resources and CPU

• US 6,591,358 B2
• Filed: 01/26/2001
• Issued: 07/08/2003
• Est. Priority Date: 01/26/2001
• Status: Expired due to Fees

• Current Assignee: Syed Kamal H. Jaffrey
• Original Assignee: Syed Kamal H. Jaffrey
• Inventors: Jaffrey, Syed Kamal H.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/770,810
• Publication Number:
  US 20020103987A1
• Time in Patent Office: 893 Days
• Field of Search: 700/3, 700/19, 710/8, 710/15, 710/104, 712/32, 713/1, 713/2, 709/327
• US Class Current: 712/32
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files

Abstract

A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices. Instead, the device microcontroller uses the embedded device driver to perform configuration and self diagnostic test as well as device operations. If the device is operational, the device microcontroller sends an identification signal to the hardware/firmware layer of the present to indicate availability of the device.

Claims

1. A computer system that eliminates a need for an operating system comprising:

a central processing unit (CPU);

a main memory;

at least one device;

a further unit that includes

a first microcontroller

a first memory containing a first set of instructions configured to cause the microcontroller to manage CPU operations,

a second microcontroller in communication with the first microcontroller; and

a second memory containing a second set of instructions configured to cause the second microcontroller to manage the at least one device;

a third microcontroller in communication with the first microcontroller;

a third memory containing a third set of instructions configured to cause the third microcontroller to manage memory operations;

a fourth microcontroller in communication with the first microcontroller; and

a fourth memory containing a fourth set of instructions configured to cause the fourth controller to manage data operations; and

a plurality of trace links connecting the further unit to the CPU, the main memory, and the device interface to facilitate communication between the further unit, the CPU, the main memory, and the device, the device comprising;

a fifth microcontroller in communication with at least the second microcontroller; and

a fifth memory containing a fifth set of instructions in the fifth memory configured to cause the fifth microcontroller to test the device and if the device is operational the fifth set of instructions is configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device.

2. The computer system as in claim 1, wherein the plurality of microcontrollers in the further unit are connected together to communicate with each other.

3. The computer system as in claim 2, wherein the further unit includes

a cross-bar switch to connect the plurality of microcontrollers.

4. The computer system as in claim 1, wherein

the fifth set of instructions in the fifth memory is further configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device includes sending device identification and required resource data.

5. The computer system as in claim 4, wherein

the second set of instructions in the second memory is further configured to cause the second microcontroller to receive the signal indicating availability of the device and allocating available resources to the device.

6. The computer system of claim 1, wherein the each microcontroller is associated with firmware and wherein the first, second, third, fourth, and fifth instruction sets are contained in associated firmware.

7. The computer system of claim 1, wherein the first microcontroller is directly linked to the CPU.