Three-dimensional memory array and method for storing data bits and ECC bits therein

• US 6,591,394 B2
• Filed: 12/22/2000
• Issued: 07/08/2003
• Est. Priority Date: 12/22/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Lee, Thomas H., Johnson, Mark G.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/747,574
• Publication Number:
  US 20020083390A1
• Time in Patent Office: 928 Days
• Field of Search: 430/22, 430/312, 430/313, 430/322, 714/763, 714/766, 257/777, 257/778, 257/686, 257/77, 257/278, 257/29.312, 257/27.026, 365/51, 365/63, 365/96, 365/225.7, 438/108, 438/107, 438/455, 438/505, 438/569, 438/796
• US Class Current: 714/766
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: H10B 99/10 Memory cells having a cross-point geometry

Abstract

A three-dimensional memory array and method for storing data bits and ECC bits therein is provided. A three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is described. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word.

Claims

1. A three-dimensional memory array comprising a plurality of memory cells arranged in a plurality of physically-independent sub-arrays and storing a word of n data bits and p ECC bits, wherein each of the n data bits and p ECC bits is stored in respective ones of the physically-independent sub-arrays.

2. The three-dimensional memory array of claim 1, wherein the three-dimensional memory array comprises a plurality of write-once memory cells.

3. The three-dimensional memory array of claim 1, wherein the three-dimensional memory array is selected from the group consisting of a semiconductor-transistor-technology-based memory array, a magnetic-based memory array, and an organic-electronic-based memory array.

4. The three-dimensional memory array of claim 1, wherein the three-dimensional memory array is part of a memory device comprising ECC code circuitry operative to generate the p ECC bits based on the n data bits.

5. The three-dimensional memory array of claim 1, wherein the memory cells are arranged in a plurality of layers of memory cells stacked vertically above one another in a single integrated circuit.

6. The three-dimensional memory array of claim 1, wherein each memory cell comprises exactly two terminals.

7. The three-dimensional memory array of claim 1, wherein the three-dimensional memory array comprises a plurality of wires comprising wordlines and bitlines, and wherein each memory cell is connected to exactly two wires:

the respective wordline and the respective bitline.

8. The three-dimensional memory array of claim 1, wherein the memory cells comprise a semiconductor material.

9. The three-dimensional memory array of claim 1, wherein the memory cells comprise a material selected from the group consisting of an organic polymer, a phase change material, and an amorphous solid.

10. The three-dimensional memory array of claim 1, wherein the memory cells store digital media information selected from the group consisting of:

digital text, digital books, digital music, digital audio, at least one digital still image, a sequence of digital images, digital video, at least one digital map, and combinations thereof.

11. The three-dimensional memory array of claim 1 in combination with a digital media storage device coupled with the three-dimensional memory array, the storage device operative to generate the p ECC bits from the n data bits.

12. The three-dimensional memory array of claim 11, wherein the storage device is selected from the group consisting of a digital camera, a digital audio playback device, and digital audio book.

13. A method for storing data bits and error checking and correcting (ECC) code bits in a three-dimensional memory array, the method comprising:

providing a three-dimensional memory array comprising a plurality of memory cells arranged in a plurality of physically-independent sub-arrays; and

storing a word of n data bits and p ECC bits in the three-dimensional memory array by storing each of the n data bits and p ECC bits in respective ones of the plurality of physically-independent sub-arrays.

14. The method of claim 13, wherein the three-dimensional memory array comprises a plurality of write-once memory cells.

15. The method of claim 13, wherein the three-dimensional memory array is selected from the group consisting of a semiconductor-transistor-technology-based memory array, a magnetic-based memory array, and an organic-electronic-based memory array.

16. The method of claim 13, wherein the three-dimensional memory array is part of a memory device comprising ECC code circuitry, and wherein the method further comprises generating the p ECC bits based on the n data bits with the ECC code circuitry.

17. The method of claim 13, wherein the memory cells are arranged in a plurality of layers of memory cells stacked vertically above one another in a single integrated circuit.

18. The method of claim 13, wherein each memory cell comprises exactly two terminals.

19. The method of claim 13, wherein the three-dimensional memory array comprises a plurality of wires comprising wordlines and bitlines, and wherein each memory cell is connected to exactly two wires:

the respective wordline and the respective bitline.

20. The method of claim 13, wherein the memory cells comprise a semiconductor material.

21. The method of claim 13, wherein the memory cells comprise a material selected from the group consisting of an organic polymer, a phase change material, and an amorphous solid.

22. The method of claim 13, wherein the memory cells store digital media information selected from the group consisting of:

digital text, digital books, digital music, digital audio, at least one digital still image, a sequence of digital images, digital video, at least one digital map, and combinations thereof.

23. The method of claim 13 further comprising generating the p ECC bits from the n data bits with a digital media storage device coupled with the three-dimensional memory array.

24. The method of claim 23, wherein the storage device is selected from the group consisting of a digital camera, a digital audio playback device, and digital audio book.

25. A memory device comprising:

a three-dimensional memory array comprising a plurality of memory cells arranged in a plurality of physically-independent sub-arrays; and

error checking and correcting (ECC) code circuitry in communication with the three-dimensional memory array;

wherein the memory device stores each bit of a word of n data bits and p ECC bits in respective ones of the physically-independent sub-arrays.

26. The memory device of claim 25, wherein the three-dimensional memory array comprises a plurality of write-once memory cells.

27. The memory device of claim 25, wherein the three-dimensional memory array is selected from the group consisting of a semiconductor-transistor-technology based memory array, a magnetic-based memory array, and an organic-electronic-based memory array.

28. The memory device of claim 25, wherein the memory cells are arranged in a plurality of layers of memory cells stacked vertically above one another in a single integrated circuit.

29. The memory device of claim 25, wherein the memory cells comprise a semiconductor material.

30. The memory device of claim 25, wherein the memory cells comprise a material selected from the group consisting of an organic polymer, a phase change material, and an amorphous solid.