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Apparatus and method for designing semiconductor circuit, and recording medium

  • US 6,591,408 B1
  • Filed: 09/26/2000
  • Issued: 07/08/2003
  • Est. Priority Date: 09/30/1999
  • Status: Expired due to Fees
First Claim
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1. A design apparatus comprising:

  • a block design unit which designs a plurality of functional blocks for a semiconductor integrated circuit, wherein clock lines and functional cells on each of said functional blocks have been laid out so that clock skew of each functional block is minimized;

    a floorplan design unit for laying out the plurality of functional blocks within a predetermined area in the semiconductor circuit;

    a wiring erasing unit which erases pre-designed clock lines in said functional blocks laid out in said predetermined area; and

    an on-circuit wiring layout design unit which determines clock line paths in said functional blocks from which said clock lines are erased, and determines clock lines among said functional blocks, so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.

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