Apparatus and method for designing semiconductor circuit, and recording medium

• US 6,591,408 B1
• Filed: 09/26/2000
• Issued: 07/08/2003
• Est. Priority Date: 09/30/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Asahina, Akihiro
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Tat, Binh C.
• Application Number:
  US09/670,461
• Time in Patent Office: 1,015 Days
• Field of Search: 716/8, 716/9, 716/10, 716/11, 716/12, 395/500.01, 364/491, 364/490
• US Class Current: 716/122
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A floorplan design unit lays out a plurality of functional blocks of a semiconductor integrated circuit in a predetermined area. Paths of clock lines in the functional blocks are designed so that clock skew of each functional block satisfies predetermined conditions. A wiring eraser erases clock lines in the functional blocks laid out in the predetermined area. An on-circuit wiring layout unit determines paths of clock lines in the functional blocks from which the clock lines are erased, and determines paths of clock lines among the functional blocks so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions. The on-circuit wiring layout unit determines the clock line paths over the semiconductor integrated circuit with targeting an upper wiring layer.

Claims

1. A design apparatus comprising:

a block design unit which designs a plurality of functional blocks for a semiconductor integrated circuit, wherein clock lines and functional cells on each of said functional blocks have been laid out so that clock skew of each functional block is minimized;

a floorplan design unit for laying out the plurality of functional blocks within a predetermined area in the semiconductor circuit;

a wiring erasing unit which erases pre-designed clock lines in said functional blocks laid out in said predetermined area; and

an on-circuit wiring layout design unit which determines clock line paths in said functional blocks from which said clock lines are erased, and determines clock lines among said functional blocks, so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.

2. The design apparatus according to claim 1, wherein said on-circuit wiring layout design unit determines clock lines over said semiconductor integrated circuit with targeting an upper wiring layer.

3. The design apparatus according to claim 2, wherein said on-circuit wiring layout design unit comprises:

a draft unit which generates a clock tree to draft paths of said clock lines; and

a path adjuster unit which adjusts said drafted paths so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.

4. The design apparatus according to claim 3, wherein said block design unit comprises:

a cell layout design unit which lays out a plurality of cells of a functional block;

an in-block wiring layout design unit which determines clock line paths in said functional block so that clock skew of said functional block satisfies predetermined conditions; and

a wiring layout design unit which determines wiring paths other than said clock line paths in accordance with timing design of said functional block.

5. A design method comprising:

designing a plurality of functional blocks of a semiconductor integrated circuit, wherein clock line paths and functional cells are laid out on each of said functional blocks so that clock skew of each functional block is minimized;

laying out the plurality of functional blocks within a predetermined area in the semiconductor circuit;

erasing pre-designed clock lines in said functional blocks laid out in the predetermined area; and

determining clock line paths in said functional blocks from which said predesigned clock lines are erased, and clock lines among said functional blocks so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.

6. The design method according to claim 5, wherein said determining clock line paths in said functional blocks and clock line paths among said functional blocks comprises determining clock line paths over said semiconductor integrated circuit with targeting an upper wiring layer.

7. The design method according to claim 6 wherein said determining clock line paths in said functional blocks and clock line paths among said functional blocks comprises:

generating a clock tree to draft paths of said clock lines; and

adjusting the drafted paths so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.

8. The design method according to claim 7, wherein said designing said functional blocks comprises:

designing layout of a plurality of cells of said functional blocks;

determining paths of clock lines in each of said functional blocks so that clock skew of each functional block satisfies predetermined conditions; and

determining paths of wiring other than said clock lines in accordance with timing design of each functional block.

9. A computer readable recording medium storing a program to be executed by a computer by which said computer functions as a design apparatus comprising:

a block design unit which designs a plurality of functional blocks for a semiconductor integrated circuit, wherein clock lines and functional cells on each of said functional blocks are laid out so that clock skew of each functional block is minimized;

a floorplan design unit for laying out the plurality of functional blocks within a predetermined area in the semiconductor integrated circuit;

a wiring erasing unit which erases pre-designed clock lines in said functional blocks laid out in said predetermined area; and

an on-circuit wiring layout design unit which determines clock line paths in said functional blocks from which said clock lines are erased, and determines clock lines among said functional blocks, so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.