Trench DMOS transistor with embedded trench schottky rectifier

• US 6,593,620 B1
• Filed: 10/06/2000
• Issued: 07/15/2003
• Est. Priority Date: 10/06/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US09/684,931
• Time in Patent Office: 1,012 Days
• Field of Search: 257/335, 257/476, 438/269, 438/576
• US Class Current: 257/335
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit includes: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (t) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.

Claims

1. An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions, said integrated circuit comprising:

a substrate of a first conductivity type;

an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower doping level than said substrate;

a plurality of body regions of a second conductivity type within said epitaxial layer in said transistor regions;

a plurality of trenches within said epitaxial layer in both said transistor regions and said rectifier regions;

a first insulating layer that lines said trenches;

a polysilicon conductor within said trenches and overlying the first insulating layer;

a plurality of source regions of said first conductivity type within said body regions adjacent to said trenches;

a second insulating layer which is disposed over and is in contact with said polysilicon conductor within said transistor regions; and

an electrode layer over both said transistor regions and said rectifier regions and which is in contact with said second insulating layer;

wherein said integrated circuit contains an epitaxial layer, and wherein said conductive layer is in contact with a portion of said epitaxial layer, in said rectifier region, which has said first conductivity type, and wherein said first and second conductivity types are diverse.

2. The integrated circuit of claim 1 wherein said substrate is an n-doped substrate.

3. The integrated circuit of claim 1 wherein the first insulating layer is a silicon dioxide layer.

4. The integrated circuit of claim 1 wherein the second insulating layer is a borophosphosilicate glass layer.

5. The integrated circuit of claim 1 further comprising an electrode layer on a surface of the substrate opposite the body regions.

6. The integrated circuit of claim 1, wherein said trench Schottky barrier rectifiers and said trench DMOS transistors are fabricated from a common oxide layer and a common polysilicon layer disposed over said oxide layer.

7. The integrated circuit of claim 1, wherein said trench Schottky barrier rectifiers and said trench DMOS transistors are fabricated using a common substrate, a common epitaxial layer disposed over said substrate, a common oxide layer disposed over said epitaxial layer, and a common polysilicon layer disposed over said oxide layer.

8. The integrated circuit of claim 7, wherein the anodes of said trench Schottky barrier rectifiers and the sources of said trench DMOS transistors share a common electrode, and wherein the cathodes of said trench Schottky barrier rectifiers and the drains of said trench DMOS transistors share a common electrode.

9. The integrated circuit of claim 1, wherein said conductive layer comprises a metal.

10. The integrated circuit of claim 1, wherein said integrated circuit contains a body region, and wherein said body region is of essentially uniform thickness.

11. The integrated circuit of claim 1, wherein the trenches of said trench Schottky barrier rectifiers and said trench DMOS transistors extend below the lowest point of the body region.

12. The integrated circuit of claim 1, wherein said integrated circuit contains a body region, and wherein the trench of at least one of said trench Schottky barrier rectifiers is not in contact with said body region.

13. The integrated circuit of claim 1, wherein said rectifier region is devoid of body dopant regions.

14. The integrated circuit of claim 1, wherein said insulating layer is not present in said rectifier region.

15. The integrated circuit of claim 1, wherein said insulating layer comprises BPSG.

16. The integrated circuit of claim 1, wherein said electrode layer extends continuously over both said transistor regions and said rectifier regions.

17. An integrated circuit, comprising:

a plurality of trench Schottky barrier rectifiers;

a plurality of trench DMOS transistors defining a transistor region;

a conductive layer which extends continuously over said trench Schottky barrier rectifiers and said trench DMOS transistors;

a body region; and

an insulating layer;

wherein said trench Schottky barrier rectifiers and said trench DMOS transistors are integrated upon a common substrate, wherein the trenches of said trench Schottky barrier rectifiers and said trench DMOS transistors contain polysilicon, wherein the insulating layer is disposed over and is in contact with said polysilicon within said transistor regions and is also in contact with said conductive layer within said transistor regions, and wherein the trench of at least one of said trench Schottky barrier rectifiers is not in contact with said body region.

18. The integrated circuit of claim 17, wherein said conductive layer is a metal layer.

19. The integrated circuit of claim 17, wherein said integrated circuit contains a body region, and wherein said body region is of essentially uniform thickness.

20. The integrated circuit of claim 17, wherein the trenches of said trench Schottky barrier rectifiers and said trench DMOS transistors extend below the lowest point of the body region.

21. The integrated circuit of claim 17, wherein said rectifier region is devoid of body dopant regions.

22. The integrated circuit of claim 17, wherein said insulating layer is not present in said rectifier region.

23. The integrated circuit of claim 17, wherein said integrated circuit contains an epitaxial layer, and wherein said conductive layer is in contact with said epitaxial layer in said rectifier region.

24. The integrated circuit of claim 17, wherein said conductive layer comprises a metal.

25. The integrated circuit of claim 17, wherein said insulating layer comprises BPSG.