Thin film transistors with vertically offset drain regions

• US 6,593,624 B2
• Filed: 09/25/2001
• Issued: 07/15/2003
• Est. Priority Date: 09/25/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Walker, Andrew J.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US09/961,278
• Publication Number:
  US 20030057435A1
• Time in Patent Office: 658 Days
• Field of Search: 257/66, 257/324, 257/344, 257/347, 257/408
• US Class Current: 257/344
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

There is provided a semiconductor device, such as a TFT, with a vertical drain offset region. The device contains a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electrode and a gate insulating layer between the gate electrode and the channel region. The device also contains a heavily doped semiconductor source region of a second conductivity type, a heavily doped semiconductor drain region of a second conductivity type. An intrinsic or lightly doped semiconductor drain offset region is located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.

Claims

1. A completed semiconductor device, comprising:

a substrate having an upper first surface;

a semiconductor channel region of a first conductivity type over the first surface;

a gate electrode;

a gate insulating layer between the gate electrode and the channel region;

a heavily doped semiconductor source region of a second conductivity type;

a heavily doped semiconductor drain region of a second conductivity type; and

an intrinsic or lightly doped semiconductor drain offset region located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.

2. The device of claim 1, wherein the gate electrode is offset from the drain region at least partially in a direction perpendicular to the first surface.

3. The device of claim 2, wherein the drain region is offset from the channel region in a direction perpendicular to the first surface.

4. The device of claim 2, wherein the drain region is offset from the channel region in both parallel and perpendicular directions to the first surface.

5. The device of claim 1, wherein the offset region comprises an intrinsic semiconductor region.

6. The device of claim 1, where the offset region comprises a lightly doped semiconductor region of the second conductivity type.

7. The device of claim 1, further comprising an intrinsic or lightly doped semiconductor source offset region of the second conductivity type located between the source region and the channel region, such that the source region is offset from the channel region at least partially in a direction perpendicular to the first surface.

8. The device of claim 1, wherein:

the first surface comprises an insulating surface;

the channel region comprises a polysilicon or an amorphous silicon layer;

the source region comprises a polysilicon layer located above or below a first portion of the channel region;

the drain region comprises a polysilicon layer located above or below a second portion of the channel region; and

the drain offset region comprises a polysilicon layer located between the channel region and the drain region.

9. The device of claim 8, further comprising a planarized insulating fill layer located between the source region and the drain region.

10. The device of claim 9, wherein:

the gate electrode and the gate insulating layer are located above the channel region; and

the source region, the drain region and the drain offset region are located below the channel region.

11. The device of claim 9, wherein:

the gate electrode and the gate insulating layer are located below the channel region; and

the source region, the drain region and the drain offset region are located above the channel region.

12. The device of claim 1, wherein:

the first surface comprises an insulating surface;

the channel region comprises a polysilicon or an amorphous silicon layer;

the source region comprises a polysilicon layer located above or below and laterally spaced from a first portion of the channel region;

the drain region comprises a polysilicon layer located above or below and laterally spaced from a second portion of the channel region; and

the drain offset region comprises a polysilicon layer located between the channel region and the drain region, and contacting a lateral edge of the channel region.

13. The device of claim 12, further comprising a planarized insulating fill layer located between the source region and the drain region.

14. The device of claim 1, further comprising:

a first metal or a metal silicide layer in contact with the source region; and

a second metal or a metal silicide layer in contact with the drain region.

15. The device of claim 1, wherein the gate insulating layer comprises a portion of a charge storage region.

16. The device of claim 15, wherein the charge storage region comprises a dielectric isolated floating gate, an ONO dielectric film or an insulating layer containing conductive nanocrystals.

17. The device of claim 1, wherein the gate electrode and the gate insulating layer extend above or below an entire length of the channel region.

18. An array of semiconductor devices comprising a plurality of semiconductor devices of claim 1.

19. The array of claim 18, wherein the array comprises:

(a) a first plurality rails disposed at a first height above the substrate in a first direction;

wherein each of the first plurality of rails comprises a heavily doped semiconductor source line of a second conductivity type;

(b) a second plurality rails disposed at the first height above the substrate in the first direction;

wherein said second plurality of rails are interspersed with and spaced apart from the first plurality of rails; and

wherein each of the second plurality of rails comprises a heavily doped semiconductor drain line of the second conductivity type and an intrinsic or a lightly doped semiconductor drain offset of the second conductivity type; and

(c) a third plurality of spaced-apart rail-stacks disposed at a second height different from the first height in a second direction different from the first direction, each rail-stack comprising;

a semiconductor layer of the first conductivity type whose first surface is in contact with the first and the second plurality of rails;

a conductive film; and

a charge storage film disposed between a second surface of the semiconductor layer and the conductive film.

20. The array of 19, wherein each semiconductor device of the array comprises:

a portion of the source line as a source region;

a portion of the drain line as a drain region;

a portion of the drain offset as a drain offset region;

a portion of the semiconductor layer between a first rail and an adjacent second rail as a channel region;

a portion of the conductive film above the channel region as the gate electrode.

21. The array of claim 20, wherein:

said semiconductor layer comprises polysilicon; and

said charge storage film is selected from a group consisting of a dielectric isolated floating gate, an ONO dielectric film, and an insulating layer containing conductive nanocrystals.

22. The array of claim 21, further comprising:

a planarized first insulating material located in a space between adjacent first and second rails; and

a planarized second insulating material located in a space between adjacent spaced-apart rail-stacks.

23. The array of claim 20, wherein the array comprises a monolithic three dimensional array of memory devices.

24. A completed array of thin film transistors, comprising:

(a) a substrate;

(b) a first plurality rails disposed at a first height above the substrate in a first direction;

wherein each of the first plurality of rails comprises a heavily doped semiconductor source line of a first conductivity type;

(c) a second plurality rails disposed at the first height above the substrate in the first direction;

wherein said second plurality of rails are interspersed with and spaced apart from the first plurality of rails; and

wherein each of the second plurality of rails comprises a heavily doped semiconductor drain line of the first conductivity type and an intrinsic or a lightly doped semiconductor drain offset of the first conductivity type; and

(d) a third plurality of spaced-apart rail-stacks disposed at a second height different from the first height in a second direction different from the first direction, each rail-stack comprising;

a semiconductor layer of a second conductivity type whose first surface is in contact with the first and the second plurality of rails;

a conductive film; and

a charge storage film disposed between a second surface of the semiconductor layer and the conductive film.

25. The array of claim 24, wherein the third plurality of spaced-apart rail-stacks are located above the first and the second plurality of rails.

26. The array of claim 24, wherein the third plurality of spaced-apart rail-stacks are located below the first and the second plurality of rails.

27. The array of claim 24 wherein a space between the first and the second rails contains a planarized deposited insulating material.

28. The array of claim 27 wherein said semiconductor in the first rails, the second rails and the third rail stacks comprises polysilicon.

29. The device of claim 24, wherein the charge storage film comprises a dielectric isolated floating gate, an ONO dielectric film or an insulating layer containing conductive nanocrystals.

30. The device of claim 24, wherein the conductive film comprises a polysilicon layer and an overlying metal silicide layer.

39. The array of claim 24, wherein the array comprises a memory array of EEPROM thin film transistors.

40. The array of claim 39, wherein:

the semiconductor layer comprises a plurality of discrete islands in the third plurality of rail stacks; and

the array comprises an array of EEPROM thin film transistors that are programmable by Fowler-Nordheim tunneling.

41. A monolithic three dimensional array of thin film transistors comprising a plurality of arrays of claim 24 separated by at least one interlayer insulating layer.

31. The array of 24, wherein each thin film transistor of the array comprises:

a portion of the source line as a source region;

a portion of the drain line as a drain region;

a portion of the drain offset as a drain offset region;

a portion of the semiconductor layer between a first rail and an adjacent second rail as a channel region;

a portion of the conductive film above the channel region as the gate electrode.

32. The device of claim 31, wherein the drain region is offset from the channel region in a direction perpendicular to the substrate.

33. The device of claim 31, wherein the drain region is offset from the channel region in both parallel and perpendicular directions to the substrate.

34. The device of claim 31, wherein the drain offset region comprises an intrinsic semiconductor region.

35. The device of claim 31, where the drain offset region comprises a lightly doped semiconductor region of the first conductivity type.

36. The device of claim 31, further comprising an intrinsic or lightly doped semiconductor source offset region of the first conductivity type located between the source region and the channel region, such that the source region is offset from the channel region at least partially in a direction perpendicular to the substrate.

37. The device of claim 31, wherein:

the source region is located above or below and laterally spaced from a first portion of the channel region;

the drain region is located above or below and laterally spaced from a second portion of the channel region; and

the drain offset region is located between the channel region and the drain region, and contacts a lateral edge of the channel region.

38. The device of claim 31, further comprising:

a first metal or a metal silicide layer in contact with the source region; and

a second metal or a metal silicide layer in contact with the drain region.

42. A method of making a semiconductor device, comprising:

providing a substrate having an insulating upper first surface;

forming a semiconductor channel region of a first conductivity type over the first surface;

forming a gate insulating layer;

forming a gate electrode such that the gate insulating layer is located between the gate electrode and the channel region;

forming a heavily doped semiconductor source region of a second conductivity type;

forming a heavily doped semiconductor drain region of the second conductivity type; and

forming an intrinsic or lightly doped semiconductor drain offset region of the second conductivity type located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.

43. The method of claim 42, wherein the gate electrode is offset from the channel region at least partially in a direction perpendicular to the first surface.

44. The method of claim 43, wherein the drain region is offset from the channel region in a direction perpendicular to the first surface.

45. The method of claim 43, wherein the drain region is offset from the channel region in both parallel and perpendicular directions to the first surface.

46. The method of claim 42, wherein the offset region comprises an intrinsic semiconductor region.

47. The method of claim 42, where the offset region comprises a lightly doped semiconductor region of the second conductivity type.

48. The method of claim 42, further comprising forming an intrinsic or lightly doped semiconductor source offset region of the second conductivity type, such that the source offset region is located between the source region and the channel region, such that the source region is offset from the channel region at least partially in a direction perpendicular to the first surface.

49. The method of claim 42, further comprising:

forming a heavily doped first polysilicon layer of the second conductivity type over the substrate;

forming an intrinsic or a lightly doped second polysilicon layer of the second conductivity type over the first polysilicon layer;

patterning the second polysilicon layer to form at least a drain offset region;

patterning the first polysilicon layer to form the source region and the drain region under the drain offset region;

forming a third polysilicon layer of a first conductivity type over the drain offset region;

patterning the third polysilicon layer to form a channel region in contact with the drain offset region;

forming a first insulating layer over the third polysilicon layer;

forming a conductive film over the first insulating layer; and

patterning the first insulating layer and the conductive film to form a gate insulating layer and a gate electrode.

50. The method of claim 49, wherein:

the step of patterning the second polysilicon layer comprises forming a drain offset region located over the drain region and forming a source offset region located over the source region;

the step of patterning the third polysilicon layer comprises forming a channel region in contact with the drain offset region and the source offset region; and

the step of forming the first insulating layer comprises forming the first insulating layer over the third polysilicon layer either before or after the step of patterning the third polysilicon layer.

51. The method of claim 49, further comprising:

patterning the second polysilicon layer to form a source offset region; and

selectively implanting ions of a second conductivity type into the source offset region to convert the source offset region into a heavily doped an upper portion of the source region of the second conductivity type.

52. The method of claim 49, wherein:

the step of forming the second polysilicon layer precedes the step of patterning the first polysilicon layer; and

the steps of patterning the first polysilicon layer and patterning the second polysilicon layer comprise etching the first and the second polysilicon layers using a same photoresist mask.

53. The method of claim 49, further comprising:

forming a second insulating layer after the step of patterning the second polysilicon layer and before the step of forming the third polysilicon layer; and

planarizing the second insulating layer by chemical mechanical polishing using the drain offset region as a polish stop such that the second insulating layer is located between the source and the drain regions.

54. The method of claim 42, further comprising:

forming a conductive film over the substrate;

forming a first insulating layer over the conductive film;

patterning the first insulating layer and the conductive film to form a gate insulating layer and a gate electrode;

forming a third polysilicon layer of a first conductivity type over the gate insulating layer;

patterning the third polysilicon layer to form a channel region;

forming a lightly doped second polysilicon layer of the second conductivity type or an intrinsic second polysilicon layer over the channel region;

forming a heavily doped first polysilicon layer of the second conductivity type over the second polysilicon layer;

patterning the second polysilicon layer to form at least a drain offset region over the channel region; and

patterning the first polysilicon layer to form the source region and to form the drain region over the drain offset region.

55. The method of claim 54, wherein:

the step of patterning the second polysilicon layer comprises forming a drain offset region over the channel region; and

the step of patterning the first polysilicon layer comprises forming the source region on the channel region and forming the drain region over the drain offset region.

56. The method of claim 54, wherein:

the step of patterning the second polysilicon layer comprises forming the drain offset region and a source offset region located over the channel region; and

the step of patterning the first polysilicon layer comprises forming the source region over the source offset region and forming the drain region over the drain offset region.

57. The method of claim 56, wherein:

the step of forming the first polysilicon layer precedes the step of patterning the second polysilicon layer; and

the steps of patterning the first polysilicon layer and patterning the second polysilicon layer comprise etching the first and the second polysilicon layers using the same photoresist mask.

58. The method of claim 54, further comprising:

forming a second insulating layer after the step of patterning the first polysilicon layer; and

planarizing the second insulating layer by chemical mechanical polishing using the source and drain regions as a polish stop such that the second insulating layer is located between the source and the drain regions.

59. The method of claim 42, further comprising:

forming a conductive film over the substrate;

forming a first insulating layer over the conductive film;

patterning the first insulating layer and the conductive film to form a gate insulating layer and a gate electrode;

forming a lightly doped second polysilicon layer of the second conductivity type or an intrinsic second polysilicon layer over the gate insulating layer;

forming a heavily doped first polysilicon layer of the second conductivity type over the second polysilicon layer;

patterning the second polysilicon layer to form at least a drain offset region over the gate insulating layer;

patterning the first polysilicon layer to form the source region and to form the drain region over the drain offset region;

forming a third polysilicon layer of a first conductivity type over the source and the drain regions and over an exposed portion of the gate insulating layer between the source and the drain regions; and

patterning the third polysilicon layer to form a channel region over the gate insulating layer and between the source and the drain regions.

60. The method of claim 59, wherein:

the step of patterning the second polysilicon layer comprises forming a drain offset region over the channel region; and

the step of patterning the first polysilicon layer comprises forming the source region on the gate insulating layer and forming the drain region over the drain offset region.

61. The method of claim 59, wherein:

the step of patterning the second polysilicon layer comprises forming the drain offset region and a source offset region over the gate insulating layer; and

the step of patterning the first polysilicon layer comprises forming the source region over the source offset region and forming the drain region over the drain offset region.

62. The method of claim 61, wherein:

the step of forming the first polysilicon layer precedes the step of patterning the second polysilicon layer; and

the steps of patterning the first polysilicon layer and patterning the second polysilicon layer comprise etching the first and the second polysilicon layers using the same photoresist mask.

63. The method of claim 59, further comprising:

forming a second insulating layer after the step of patterning the third polysilicon layer; and

planarizing the second insulating layer by chemical mechanical polishing using the source and drain regions as a polish stop such that the second insulating layer is located between the source and the drain regions.

64. The method of claim 42, wherein the steps of forming the source region, the drain region and the drain offset region comprise:

forming a second insulating layer;

forming openings in the second insulating layer;

forming a heavily doped first polysilicon layer of a second conductivity type and an intrinsic or lightly doped polysilicon layer of a second conductivity type in the openings; and

chemically-mechanically planarizing the first and the second polysilicon layers such that the source region is formed in a first opening and the drain region and the drain offset region are formed in a second opening.

65. The method of claim 42, wherein the steps of forming the source region, the drain region and the drain offset region comprise:

forming a patterned intrinsic or lightly doped polysilicon layer of the second conductivity type;

forming an insulating layer between patterned portions of the polysilicon layer;

implanting ions of the second conductivity type at least into upper portions of the polysilicon layer; and

performing an activation anneal to form the source and drain regions in the upper portions of the polysilicon layer and at least a drain offset region in a lower portion of the polysilicon layer.

66. The method of claim 42, wherein the gate insulating layer comprises a portion of a charge storage region.

67. The method of claim 42, further comprising:

forming a heavily doped first polysilicon layer of the second conductivity type over the substrate;

forming a lightly doped second polysilicon layer of the second conductivity type or an intrinsic second polysilicon layer over the first polysilicon layer;

patterning the second polysilicon layer to form at least a plurality of drain offset regions;

patterning the first polysilicon layer to form a first plurality of rails comprising a plurality of source regions and to form a second plurality of rails comprising a plurality of drain regions under the drain offset regions;

forming a third polysilicon layer of a first conductivity type over the plurality of the drain offset regions;

forming a first insulating layer over the third polysilicon layer;

forming a conductive film over the first insulating layer; and

patterning the third polysilicon layer, the first insulating layer and the conductive film to form a plurality of spaced-apart rail stacks each comprising the channel region, the gate insulating layer and the gate electrode.

68. The method of claim 67, further comprising patterning the third polysilicon layer to form a plurality of strips prior to patterning the third polysilicon layer to form a plurality of spaced-apart rail stacks, such that the channel regions in the rail stacks comprise polysilicon islands.

69. The method of claim 67, wherein:

the step of patterning the second polysilicon layer comprises forming the plurality of drain offset regions over the drain regions and forming a plurality of source offset regions over the source regions; and

the step of patterning the third polysilicon layer comprises forming a plurality of channel regions in contact with the plurality of the drain offset regions and the plurality of the source offset regions.

70. The method of claim 42, further comprising:

forming a conductive film over the substrate;

forming a first insulating layer over the conductive film;

forming a third polysilicon layer of a first conductivity type over the first insulating layer;

patterning the third polysilicon layer, the first insulating layer and the conductive film to form a plurality of spaced-apart rail stacks each comprising the channel region, the gate insulating layer and the gate electrode;

forming a lightly doped second polysilicon layer of the second conductivity type or an intrinsic second polysilicon layer over the spaced-apart rail stacks;

forming a heavily doped first polysilicon layer of the second conductivity type over the second polysilicon layer;

patterning the second polysilicon layer to form a plurality of drain offset regions; and

patterning the first polysilicon layer to form a first plurality of rails comprising a plurality of source regions and to form a second plurality of rails comprising a plurality of drain regions over the drain offset regions.

71. The method of claim 70, wherein:

the step of patterning the second polysilicon layer comprises forming a plurality of the drain offset regions and a plurality of source offset regions over the rail stacks; and

the step of patterning the first polysilicon layer comprises forming a plurality of the source regions over the source offset regions and forming a plurality of the drain regions over the drain offset regions.