Semiconductor device and method of manufacturing the same

• US 6,593,634 B2
• Filed: 04/12/2001
• Issued: 07/15/2003
• Est. Priority Date: 04/13/2000
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group), Tadahiro Ohmi
• Original Assignee: Seiko Epson Corporation (Seiko Group), Tadahiro Ohmi
• Inventors: Ohmi, Tadahiro, Shimada, Hiroyuki
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): Fenty, Jesse A
• Application Number:
  US09/834,992
• Publication Number:
  US 20030052378A1
• Time in Patent Office: 824 Days
• Field of Search: 257/412, 257/413, 257/353, 257/354, 257/761
• US Class Current: 257/412
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A semiconductor device includes an NMOSFET and a PMOSFET. Each MOSFET includes first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like, a channel region formed between the first and second impurity diffusion layers, a gate insulation layer at least formed on the channel region, and a gate electrode formed on the gate insulation layer. The gate electrode includes a tantalum nitride layer in a region in contact with at least the gate insulation layer. The semiconductor device exhibits high current drive capability and can be manufactured at high yield.

Claims

1. A semiconductor device comprising:

first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer;

a channel region formed between the first and second impurity diffusion layers;

a gate insulation layer formed at least on the channel region; and

a gate electrode formed on the gate insulation layer,

wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer and a body-centered cubic tantalum layer heteroepitaxially formed over the tantalum nitride layer,

wherein a nitrogen/tantalum ratio (x) as shown by TaN_x in the tantalum nitride layer is 0.25 to 1.0.

2. The semiconductor device according to claim 1,

wherein the nitrogen/tantalum ratio (x) shown by TaN_x in the tantalum nitride layer is approximately 0.5.

3. The semiconductor device according to claim 1,

wherein the tantalum nitride layer has a thickness of 1 nm to 300 nm.

4. The semiconductor device according to claim 1,

wherein the gate electrode further comprises a cap layer formed on the uppermost layer.

5. The semiconductor device according to claim 4,

wherein the cap layer is formed of at least one material selected from TaN_x, TaSi_xN_y, TiN_x, TiAl_xN_y, Si, and silicide of a transition metal.

6. The semiconductor device according to claim 5, wherein the cap layer is formed of the tantalum nitride layer.

7. The semiconductor device according to claim 1,

wherein suicide layers are formed on part of the first and second impurity diffusion layers.

8. The semiconductor device according to claim 1,

wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure.

9. A complementary semiconductor device comprising an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor,

wherein each of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor comprises:

first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer;

a channel region formed between the first and second impurity diffusion layers;

a gate insulation layer formed on the channel region; and

a gate electrode formed on the gate insulation layer,

wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer and a body-centered cubic tantalum layer heteroepitaxially formed over the tantalum nitride layer,

wherein a nitrogen / tantalum ratio (x) as shown by TaN_x in the tantalum nitride layer is 0.25 to 1.0.

10. The complementary semiconductor device according to claim 9,

wherein the nitrogen/tantalum ratio (x) shown by TaN_x in the tantalum nitride layer is approximately 0.5.

11. The complementary semiconductor device according to claim 9,

wherein the tantalum nitride layer has a thickness of 1 nm to 300 nm.

12. The complementary semiconductor device according to claim 9,

wherein the gate electrode further comprises a cap layer formed on the uppermost layer.

13. The complementary semiconductor device according to claim 12,

wherein the cap layer is formed of at least one material selected from TaN_x, TaSi_xN_y, TiN_x, TiAl_xN_y, Si, and silicide of a transition metal.

14. The complementary semiconductor device according to claim 13, wherein the cap layer is formed of the tantalum nitride layer.

15. The complementary semiconductor device according to claim 9,

wherein silicide layers are formed on part of the first and second impurity diffusion layers.

16. The complementary semiconductor device according to claim 9,

wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure.