Bipolar transistor and methods of forming bipolar transistors

• US 6,593,640 B1
• Filed: 04/01/2002
• Issued: 07/15/2003
• Est. Priority Date: 04/01/2002
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Kalnitsky, Alexander, Uppili, Sudarsan
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/114,526
• Time in Patent Office: 470 Days
• Field of Search: 438/309, 438/312, 438/365, 438/366, 438/367, 438/368, 438/369, 438/520, 257/565, 257/571, 257/572, 257/588, 257/592
• US Class Current: 257/565
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence

Abstract

A bipolar transistor comprises a base region and an an extrinsic base region being located generally adjacent to the base region. The extrinsic base region has implanted therein a dopant and a dopant diffusion-retarding substance. The dopant diffusion-retarding substance serves to reduce the diffusion of the dopant into the base region. Preferably, the dopant and diffusion-retarding substances are implanted such that there is a buffer zone in the extrinsic base region immediately adjacent to the base region into which the dopant may diffuse after implantation. The dopant may for example be boron, and the dopant diffusion-retarding substance may for example be a group IV element such as carbon or germanium.

Claims

1. A bipolar transistor comprising:

a first polysilicon region formed on a semiconductor substrate,

a second base region formed on the semiconductor substrate, the first polysilicon region being located generally adjacent to the second base region in a direction parallel to a general plane of the semiconductor substrate,

the first polysilicon region including therein a dopant and a dopant diffusion retarding substance, and

a buffer zone that has a significantly less amount of the dopant as compared to an amount of the dopant in the first polysilicon region, the buffer zone being between the first polysilicon region and the second base region.

2. The transistor of claim 1 wherein

a diffusion distance for the buffer zone is based on an expected reduced diffusion as a result of the presence in the first polysilicon region of the dopant diffusion-retarding substance.

3. The transistor of claim 2 further comprising:

,

a third emitter region formed of semiconductor material, wherein the buffer zone is defined by an overlap between the third emitter region and the first polysilicon region.

4. The transistor of claim 3 wherein the dopant diffusion-retarding substance is a group IV element.

5. The transistor of claim 4 wherein the dopant diffusion-retarding substance is carbon or germanium.

6. The transistor of claim 1 wherein the dopant diffusion-retarding substance is a group IV element.

7. The transistor of claim 6 wherein the dopant diffusion-retarding substance is carbon or germanium.

8. A bipolar transistor comprising:

a base region,

an extrinsic base region being located generally adjacent to the base region,

the extrinsic base region having implanted therein a dopant and a dopant diffusion-retarding substance, the dopant and dopant diffusion-retarding substance being implanted such that there is a buffer zone in the extrinsic base region, immediately adjacent to the base region, that has a significantly less amount of the dopant as compared to an amount of the dopant in the extrinsic base region.

9. The transistor of claim 8 wherein the buffer region is defined by an overhang of an emitter region over the base region.

10. The transistor of claim 8 wherein the dopant diffusion-retarding substance is a group IV element.

11. The transistor of claim 10 wherein the dopant diffusion-retarding substance is carbon or germanium.