Power saving circuitry using predictive logic

• US 6,593,773 B2
• Filed: 09/28/2001
• Issued: 07/15/2003
• Est. Priority Date: 04/25/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leipold, Dirk, Staszewski, Robert B.
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US09/967,275
• Publication Number:
  US 20020158662A1
• Time in Patent Office: 655 Days
• Field of Search: 326/46, 326/93, 327/33, 327/271, 327/141, 327/144, 327/145, 327/12, 327/3, 327/158, 327/107, 377/24, 377/20
• US Class Current: 326/46
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H04L 7/0029 interpolation of received data signal

Abstract

To conserve power in a circuit where a high-speed signal HSIG controls combinational logic (10), while a low-speed signal LCLK drives a logic/memory circuit (12) that samples the output of the combinational logic, predictive logic state machine (14) generates a clock, P_LCLK, which has an active level preceding the active edge of LCLK by a period sufficient to allow the combinational logic to reach the desired state prior to the active edge of LCLK and, preferably, allows for possible jitter in LCLK. Responsive to P_LCLK, the signal suspend circuitry (16) either passes HSIG or gates off HSIG. Further reductions in power can be accomplished by predicting which portions of the logic/memory circuit (12) will be used, and clocking those portions.

Claims

1. A method of performing a time-to-digital conversion between edges of a first signal and a second signal, wherein said first signal transitions between states rapidly with respect to said second signal, comprising the steps of:

passing said first signal to a string of logic devices during a time period sufficient to allow the first circuit to reach a desired state prior to an active edge of the second signal and not passing the first signal to the string of logic devices during other time periods;

storing a state associated with said string of logic devices responsive to the active edge of the second signal.

2. The method of claim 1 wherein the first signal is a high frequency clock signal.

3. The method of claim 2 wherein said second signal is a clock signal of lower frequency than said first signal.

4. The method of claim 1 wherein said passing step comprises the step of passing said first signal to a string of inverters during predetermined time periods where the active edge of said second signal may occur.

5. The method of claim 1 wherein said storing step comprises the step of storing the state in a plurality of storage devices coupled to the outputs of said logic devices at the active edge of said second signal.

6. The method of claim 5 wherein said storing step comprises the step of storing the outputs of selected ionic devices in a set of respective storage devices at the active edge of said second signal.

7. The method of claim 1 and further comprising the step of predicting a time period within which a next occurrence of an active edge of said second signal will occur.

8. A method of performing a time-to-digital conversion between edges of a first signal and a second signal, wherein said first signal transitions between states rapidly with respect to said second signal, comprising the steps of:

passing said first signal to a string of logic devices during a time period sufficient to allow the string logic devices to reach the desired state prior to an active edge of the second signal and not passing the first signal to the string of logic devices during other time periods; and

storing a state, associated with said string of selected logic devices responsive to the active edge of the second signal, in a set of respective storage devices coupled to outputs of said logic devices, at the active edge of said second signal, said set of respective storage devices being selected based on a prediction of a propagation of an edge of said first signal through said string of logic devices at the active edge of said second signal.

9. A time-to-digital converter, comprising:

circuitry for receiving a first signal;

circuitry for receiving a second signal, wherein said first signal transitions between states rapidly with respect to said second signal;

a string of logic devices responsive to state transitions of said first signal;

circuitry for determining a time difference between one or more edges of said first signal relative to an active edge of said second signal responsive to a state associated with said string of logic devices at the active edge of a second signal; and

circuitry for preventing state transitions of said first signal causing transitions in said string of logic devices during periods between active edges of said second signal.

10. The time-to-digital converter of claim 9 wherein said first signal is a high frequency clock signal.

11. The time-to-digital converter of claim 10 wherein said second signal is a clock signal of lower frequency than said first signal.

12. The time-to-digital converter of claim 9 wherein said string of logic devices comprises a string of inverters.

13. The time-to-digital converter of claim 9 wherein said circuitry for determining a time difference includes a plurality of storage devices coupled to the outputs of said logic devices for storing the outputs of said logic devices at an active edge of said second signal.

14. The time-to-digital converter of claim 13 wherein a set of said storage devices store the output of respective logic devices at the active edge of said second signal.

15. The time-to-digital converter of claim 14 wherein said circuitry for determining a time difference further includes circuitry for selecting said set of storage devices based on a prediction of a propagation of an edge of said first signal through said string of logic devices at the active edge of said second signal.

16. A time-to-digital converter, comprising:

circuitry for receiving a first signal;

circuitry for receiving a second signal, wherein said first signal transitions between states rapidly with respect to said second signal;

a string of logic devices responsive to state transitions of said first signal;

circuitry for determining a time difference between one or more edges of said first signal relative to an active edge of said second signal responsive to a state associated with said string of logic devices at the active edge of a second signal; and

circuitry for preventing state transitions of said first signal causing transitions in said string of logic devices during periods between active edges of said second signal and for passing said first signal to said second signal responsive to said time period.

17. The time-to-digital converter of claim 16 wherein said circuitry for preventing state transitions further comprises circuitry for passing said first signal to said second signal responsive to said time period.

18. A method of conserving energy in a circuit comprising a first circuit of combination logic and a second circuit, wherein said first circuit is responsive to a first signal and said second circuit is responsive to a state of said first circuit at an active edge of the second signal, wherein said first signal transitions between states rapidly with respect to said second signal, comprising the steps of:

passing the first signal to the first circuit during a time period sufficient to allow the first circuit to reach a desired state prior to the active edge of the second signal and not passing the first signal to the first circuit during other time periods; and

using state information from said first circuit in said second circuit responsive to the active edge of the second signal.

19. A method of conserving energy in a circuit comprising a first circuit of combination logic and a second circuit, wherein said first circuit is responsive to a first signal and second circuit is responsive to a state of said first circuit at an active edge of the second signal, wherein said first signal transition between states rapidly with respect to said second signal, comprising the steps of:

passing the first signal to the first circuit during a time period sufficient to allow the first circuit to reach a desired state prior to the active edge of the second signal and not passing the first signal to the first circuit during other time periods;

using state information from said first circuit in said second circuit responsive to the active edge of the second signal; and

predicting which portions of said second circuit will be used.

20. A method of performing a time-to-digital conversion between edges of a first signal and a second signal, wherein said first signal transitions between states rapidly with respect to said second signal, comprising the steps of:

passing said first signal to a string of logic devices;

predicting a location of a transition of said first signal as propagated through said string of logic devices;

storing a state associated with a predetermined set of said string of logic devices around said predicted location responsive to the active edge of the second signal.

21. The method of claim 20 wherein the number of logic devices in said predetermined set is increased if a transition is not observed.

22. The method of claim 20 wherein the number of logic devices in said predetermined set is decreased if a transition is observed and more than a predetermined optimum number of logic devices are in said set.

23. The method of claim 20 wherein said predicting step comprises the step of using a fractional-N value of a frequency division ratio between said first signal and said second signal.

24. The method of claim 23 wherein said predicting step further comprises the step of predicting a location based on the fractional-N value and a previously detected transition location.

25. Circuitry for performing a time-to-digital conversion between edges of a first signal and a second signal, wherein said first signal transitions between states rapidly with respect to said second signal, comprising:

a string of logic devices through which a first signal is propagated;

circuitry predicting a location of a transition of said first signal as propagated through said string of logic devices;

storage circuits for storing output states of respective logic devices; and

circuitry for enabling a predetermined set of said storage circuits associated with logic devices around said predicted location responsive to the active edge of the second signal.

26. The circuitry of claim 25 wherein the number of storage circuits in said predetermined set is increased if a transition is not observed.

27. The circuitry of claim 25 wherein the number of storage circuits in said predetermined set is decreased if a transition is observed and more than a predetermined optimum number of storage circuits are in said set.

28. The circuitry of claim 25 wherein said predicting circuitry comprises circuitry for calculating a fractional-N value of a frequency division ratio between said first signal and said second signal.

29. The circuitry of claim 28 wherein said predicting circuitry further comprises circuitry for predicting a location based on the fractional-N value and a previously detected transition location.

30. A method, comprising the steps of:

performing a time-to-digital conversion between edges of a first signal and a second signal, wherein said first signal transitions between states rapidly with respect to said second signal; and

passing said first signal to a string of logic devices in a circuit during a time period sufficient to allow the circuit to each a desired state prior to an active edge of the second signal and not passing the first signal to the string of logic devices during other time periods.

31. The method of claim 30, further comprising the step of storing a state associated with said string of logic devices responsive to the active edge of the second signal.

33. The method of claim 30, wherein said first signal is a high frequency clock signal and said second signal is a clock signal flower frequency than said first signal.

32. A method, comprising the steps of:

performing a time-to-digital conversion between edges of a first signal and a second signal, wherein said first signal transition between states rapidly with respect to said second signal;

passing said first signal to a string of logic devices in a circuit during a time period sufficient to allow the circuit to reach a desired state prior to an active edge of second signal and not passing the first signal to the string of logic devices during other time period and

predicting a time period within which a next occurrence of an active edge of said second signal will occur.

34. A telecommunication device, comprising:

a baseband controller; and

a transceiver coupled to d baseband controller, said transceiver further comprising circuitry for performing a time-to-digital conversion between edges of a first signal and a second signal, wherein said first signal transitions between states rapidly with respect to said second signal, comprising;

a string of logic devices through which a first signal is propagated;

circuitry predicting location of a transition of said first signal as propagated through said string of logic devices;

storage circuits for string output states of respective logic devices; and

circuitry for enabling a predetermined set of said storage circuits associated with logic devices around said predicted location responsive to the active edge of the second signal.

35. A telecommunication device, comprising:

a baseband controller;

an

a transceiver coupled to said baseband controller, said transceiver further comprising a time-to-digital converter, comprising;

circuitry for receiving a first signal;

circuitry for receiving a second signal, wherein said first signal transitions between states rapidly with respect to said second signal;

a string of logic devices responsive to state transitions of said first signal;

circuitry for determining a time difference between one or more edges of said first signal relative to an active edge of said second signal responsive to a state associated with said string of logic devices at the active edge of a second signal; and

circuitry for preventing state transitions of said first signal causing transitions in said string of logic devices during periods between active edges of said second signal.