Phase-locked loop circuit

• US 6,593,787 B2
• Filed: 07/08/2002
• Issued: 07/15/2003
• Est. Priority Date: 07/13/1999
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Kouzuma, Shinichi
• Primary Examiner(s): NGUYEN, MINH T
• Application Number:
  US10/189,382
• Publication Number:
  US 20020167347A1
• Time in Patent Office: 372 Days
• Field of Search: 327/144, 327/146-148, 327/150, 327/155-160, 375/373-376, 331/1.A, 331/25, 331/16, 331/11, 331/12, 331/DIG.2
• US Class Current: 327/159
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A phase-locked loop ciruit having two requency dividing circuits which are reset in response to reset signals. The reset signals are produced by second and third frequency divided signal generated by combining the divided frequency of a reference clock signal and an output signal from a voltage controlled oscillator. The phase-locked loop ciruit adjusts rapidly the frquency and the phase of the output signal of the voltage controlled oscillator to correspond to that of the reference clock signal.

Claims

1. A phase-locked loop circuit comprising:

a first phase comparator having an output and first and second input terminals, a first frequency divided signal being input to the first input terminal of said first phase comparator and a second frequency divided signal being input to the second input terminal of said first phase comparator, said first phase comparator comparing a phase of said first frequency divided signal with a phase of said second frequency divided signal and outputting a first phase comparator output signal, said first frequency divided signal being generated by dividing the frequency of a reference clock signal;

a second phase comparator having an output and first and second input terminals, an inversion of said first frequency divided signal being input to the first input terminal of said phase comparator and a third frequency divided signal being input to the second input terminal of said second phase comparator, said second phase comparator comparing a phase of the inversion of said first frequency divided signal with a phase of said third frequency divided signal and outputting a second phase comparator output signal;

a low-pass filter having an output and first and second inputs, the first and second inputs of said low-pass filter being coupled to the outputs of said first and second phase comparators respectively, said low-pass filter outputting a signal determined by said first and second phase comparator output signals;

a voltage controlled oscillator having an output terminal and an input coupled to the output of said low-pass filter, said voltage controlled oscillator generating at the output terminal thereof an oscillator pulse signal having a frequency determined by the output of said low-pass filter;

a first frequency dividing circuit including

a first N-ary counter, said first N-ary counter having an output terminal, an input terminal coupled to the output terminal of said voltage controlled oscillator and a reset terminal; and

a first latch circuit, said first latch circuit having an output coupled to the second input terminal of said first phase comparator for inputting said second frequency divided signal thereto, a reset input pin coupled to the output terminal of said first N-ary counter, and a set input pin coupled to the reset terminal of said first N-ary counter;

a second frequency dividing circuit including

a second N-ary counter, said second N-ary counter having an output terminal, an input terminal coupled to the output terminal of said voltage controlled oscillator and a reset terminal; and

a second latch circuit, said second latch circuit having an output coupled to the second input terminal of said second phase comparator for inputting said third frequency divided signal thereto, a reset input pin coupled to the output terminal of said second N-ary counter, and a set input pin coupled to the reset terminal of said second N-ary counter; and

a reset signal circuit for applying, when a change in said oscillator pulse signal follows a change in said first frequency divided signal, first and second set signals to the set input pins of said first and second latch circuits respectively and to the reset terminals of said first and second N-ary counters respectively said first set signal generating at the output of said first latch circuit said second frequency divided signal at a first level, and said second set signal generating at the output of said second latch circuit said third frequency divided signal at a second level, said first and second set signals further initiating counting by said first and second N-ary counters of a predetermined number of pulses of said oscillator pulse signal, said first and second N-ary counters inputting reset signals to the reset input pins of said first and second latch circuits respectively when said predetermined number of pulses of said oscillator pulse signal have been counted, whereby said second frequency divided signal changes from said first level to said second level and said third frequency divided signal changes from said second level to said first level.

2. A phase-locked loop circuit as claimed in claim 1, further comprising a lock detecting circuit which outputs a lock detecting signal when a phase difference between said first frequency divided signal and said second frequency divided signal falls within one clock cycle of the oscillator pulse signal generated by said voltage controlled oscillator.

3. A phase-locked loop circuit as claimed in claim 2, wherein said lock detecting circuit includes a first latch circuit, a second latch circuit, a third latch circuit, a fourth latch circuit, and a gate circuit, said first latch circuit storing a voltage of prescribed level in response to said first frequency divided signal and being reset in response to an output signal of said second latch circuit, said second latch circuit storing an output signal of said first latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, said third latch circuit storing a voltage of prescribed level in response to said second frequency divided signal and being reset in response to an output signal of said fourth latch circuit, said fourth latch circuit storing an output signal of said third latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, and said gate circuit outputting said lock detecting signal as a result of an AND operation on the output signal of said second latch circuit and the output signal of said fourth latch circuit.

4. A phase-locked loop circuit as claimed in claim 2, wherein said lock detecting circuit includes a first latch circuit, a second latch circuit, a third latch circuit, a fourth latch circuit, a fifth latch circuit, a sixth latch circuit, and a gate circuit, said first latch circuit storing a voltage of prescribed level in response to said first frequency divided signal and being reset in response to an output signal of said second latch circuit, said second latch circuit storing an output signal of said first latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, said third latch circuit storing a voltage of prescribed level in response to said second frequency divided signal and being reset in response to an output signal of said fourth latch circuit, said fourth latch circuit storing an output signal of said third latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, each of said fifth and sixth latch circuits storing the output signal of said fourth latch circuit in response to the output signal of said second latch circuit, and said gate circuit outputting said lock detecting signal as a result of an OR operation on an output signal of said fifth latch circuit and an output signal of said sixth latch circuit.

5. A phase-locked loop circuit as claimed in claim 2, wherein said lock detecting circuit includes a first latch circuit, a second latch circuit, a third latch circuit, a fourth latch circuit, a fifth latch circuit, a sixth latch circuit, and a gate circuit, said first latch circuit storing a voltage of prescribed level in response to said first frequency divided signal and being reset in response to an output signal of said second latch circuit, said second latch circuit storing an output signal of said first latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, said third latch circuit storing a voltage of prescribed level in response to said second frequency divided signal and being reset in response to an output signal of said fourth latch circuit, said fourth latch circuit storing an output signal of said third latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, said fifth latch circuit storing the output signal of said second latch circuit in response to the output signal of said fourth latch circuit, said sixth latch circuit storing the output signal of said fourth latch circuit in response to the output signal of said second latch circuit, and said gate circuit outputting said lock detecting signal result of an OR operation on an output signal of said fifth latch circuit an output signal of said sixth latch circuit.

6. A phase-locked loop circuit as claimed in claim 2, wherein said lock detecting circuit includes a first latch circuit, a second latch circuit, a third latch circuit, a fourth latch circuit, a fifth latch circuit, a sixth latch circuit, a seventh latch circuit, an eighth latch circuit, a first multiplexer, a second multiplexer, and a gate circuit, said first latch circuit storing a voltage of prescribed level in response to said first frequency divided signal and being reset in response to an output signal of said fifth latch circuit, said second latch circuit storing an output signal of said first latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, said third latch circuit storing a voltage of prescribed level in response to said second frequency divided signal and being reset in response to an output signal of said sixth latch circuit, said fourth latch circuit storing an output signal of said third latch circuit in response to the oscillator pulse signal of said voltage controlled oscillator, said first multiplexer outputting the output signal of said first latch circuit or an output signal of said second latch circuit in response to said lock detecting signal, said second multiplexer outputting the output signal of said third latch circuit or an output signal of said fourth latch circuit in response to said lock detecting signal, said fifth latch circuit storing the output signal of said first multiplexer in response to the oscillator pulse signal of said voltage controlled oscillator, said sixth latch circuit storing the output signal of said second multiplexer in response to the oscillator pulse signal of said voltage controlled oscillator, said seventh latch circuit storing the output signal of said fifth latch circuit in response to the output signal of said sixth latch circuit, said eighth latch circuit storing the output signal of said sixth latch circuit in response to the output signal of said fifth latch circuit, and said gate circuit outputting said lock detecting signal which is a result of an OR operation on an output signal of said seventh latch circuit and an output signal of eighth latch circuit.

7. A phase-locked loop circuit as claimed in claim 2, wherein said lock detecting circuit includes a first delay circuit, a second delay circuit, a first gate circuit, a second gate circuit, and a third gate circuit, said first delay circuit outputting a first signal which delays said first frequency divided signal, said second delay circuit outputting a second signal which delays said second frequency divided signal, said first gate circuit outputting a third signal which is a result of an AND operation on an inversion of said first frequency divided signal and said first signal, said second gate circuit outputting a fourth signal which is a result of an AND operation on an inversion of said second frequency divided signal and said second signal, and said third gate circuit outputting said lock detecting signal which is a result of an AND operation on said third and fourth signals.

8. A phase-locked loop circuit as claimed in claim 2, wherein said lock detecting circuit includes a first delay circuit, a second delay circuit, a first gate circuit, a second gate circuit, and a third gate circuit, a first latch circuit, and a second latch circuit, said first delay circuit outputting a first signal which delays said first frequency divided signal, said second delay circuit outputting a second signal which delays said second frequency divided signal, said first gate circuit outputting a third signal which is a result of an AND operation on an inversion of said first frequency divided signal and said first signal, said second gate circuit outputting a fourth signal which is a result of an AND operation on an inversion of said second frequency divided signal and said second signal, said third gate circuit outputting a fifth signal which is a result of an AND operation of said third and fourth signals, said first latch circuit outputting a sixth signal of prescribed level in response to said third signal and being reset in response to said fifth signal, and said second latch circuit storing said sixth signal in response to said third signal and outputting said lock detecting signal.

9. A phase-locked loop circuit as claimed in claims 1, wherein said reset signal circuit comprises

first latch circuit means for storing said first frequency divided signal for a first predetermined period of time and outputting a first signal upon receiving said oscillator pulse signal from said voltage controlled oscillator;

second latch circuit means for storing said first signal for a second predetermined period of time and outputting a second signal upon receiving the oscillator pulse signal from said voltage controlled oscillator;

first gate circuit means for ANDing said first signal and an inversion of said second signal, the output of said first gate circuit means being applied to the reset terminal of said first N-ary counter and to the set input pin of said first latch circuit; and

second gate circuit means for ANDing an inversion of said first signal and said second signal, the output of second gate circuit means being applied to the reset terminal of said second N-ary counter and to the set input pin of said second latch circuit.

10. A phase-locked loop circuit as claimed in claim 9 wherein said reset signal circuit further comprises third latch circuit means for dividing the frequency of the reference clock signal and outputting said first frequency divided signal to said first latch circuit means and to said first phase comparator, the inversion of said first frequency divided signal being outputted to said second phase comparator.

11. A phase-locked loop circuit as claimed in claims 10, wherein said reset signal circuit further comprises

a third gate circuit means for receiving the output of said first gate circuit means and a rest input signal, the output of said third gate circuit means being coupled to the reset terminal of said first N-ary counter ;

and

a fourth gate circuit means for receiving the output of said second gate circuit means and the reset input signal, the output of said fourth gate circuit means being coupled to the reset terminal of said second N-ary counter.