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Phase-locked loop circuit

  • US 6,593,787 B2
  • Filed: 07/08/2002
  • Issued: 07/15/2003
  • Est. Priority Date: 07/13/1999
  • Status: Expired due to Term
First Claim
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1. A phase-locked loop circuit comprising:

  • a first phase comparator having an output and first and second input terminals, a first frequency divided signal being input to the first input terminal of said first phase comparator and a second frequency divided signal being input to the second input terminal of said first phase comparator, said first phase comparator comparing a phase of said first frequency divided signal with a phase of said second frequency divided signal and outputting a first phase comparator output signal, said first frequency divided signal being generated by dividing the frequency of a reference clock signal;

    a second phase comparator having an output and first and second input terminals, an inversion of said first frequency divided signal being input to the first input terminal of said phase comparator and a third frequency divided signal being input to the second input terminal of said second phase comparator, said second phase comparator comparing a phase of the inversion of said first frequency divided signal with a phase of said third frequency divided signal and outputting a second phase comparator output signal;

    a low-pass filter having an output and first and second inputs, the first and second inputs of said low-pass filter being coupled to the outputs of said first and second phase comparators respectively, said low-pass filter outputting a signal determined by said first and second phase comparator output signals;

    a voltage controlled oscillator having an output terminal and an input coupled to the output of said low-pass filter, said voltage controlled oscillator generating at the output terminal thereof an oscillator pulse signal having a frequency determined by the output of said low-pass filter;

    a first frequency dividing circuit including a first N-ary counter, said first N-ary counter having an output terminal, an input terminal coupled to the output terminal of said voltage controlled oscillator and a reset terminal; and

    a first latch circuit, said first latch circuit having an output coupled to the second input terminal of said first phase comparator for inputting said second frequency divided signal thereto, a reset input pin coupled to the output terminal of said first N-ary counter, and a set input pin coupled to the reset terminal of said first N-ary counter;

    a second frequency dividing circuit including a second N-ary counter, said second N-ary counter having an output terminal, an input terminal coupled to the output terminal of said voltage controlled oscillator and a reset terminal; and

    a second latch circuit, said second latch circuit having an output coupled to the second input terminal of said second phase comparator for inputting said third frequency divided signal thereto, a reset input pin coupled to the output terminal of said second N-ary counter, and a set input pin coupled to the reset terminal of said second N-ary counter; and

    a reset signal circuit for applying, when a change in said oscillator pulse signal follows a change in said first frequency divided signal, first and second set signals to the set input pins of said first and second latch circuits respectively and to the reset terminals of said first and second N-ary counters respectively said first set signal generating at the output of said first latch circuit said second frequency divided signal at a first level, and said second set signal generating at the output of said second latch circuit said third frequency divided signal at a second level, said first and second set signals further initiating counting by said first and second N-ary counters of a predetermined number of pulses of said oscillator pulse signal, said first and second N-ary counters inputting reset signals to the reset input pins of said first and second latch circuits respectively when said predetermined number of pulses of said oscillator pulse signal have been counted, whereby said second frequency divided signal changes from said first level to said second level and said third frequency divided signal changes from said second level to said first level.

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