Serializer

• US 6,593,863 B2
• Filed: 12/05/2001
• Issued: 07/15/2003
• Est. Priority Date: 12/05/2001
• Status: Expired due to Term

• Current Assignee: Bay Microsystems, Inc. (Vcinity, Inc.)
• Original Assignee: Parama Networks, Inc. (Vcinity, Inc.)
• Inventors: Pitio, Walter Michael
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam
• Application Number:
  US10/011,938
• Publication Number:
  US 20030102992A1
• Time in Patent Office: 587 Days
• Field of Search: 341/101, 341/61, 341/67, 341/87, 341/107, 702/119, 710/1, 714/798, 375/354, 375/350
• US Class Current: 341/101
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A method for serializing bits without introducing glitches (i.e., spurious signals) into the serialized data stream is disclosed. Furthermore, the embodiments of the present invention do not require a timing signal (e.g., a clock signal, etc.) at the frequency of the serialized data stream. On the contrary, the illustrative embodiment of the present invention requires timing signals with a frequency equal to the rate at which words are loaded into the serializer. The illustrative embodiment comprises: a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform; a second umanimity gate for generating a fourth binary waveform based on a second coincidence function of the first binary waveform and a fifth binary waveform; and a first temporal delay device for receiving the fourth binary waveform and for generating the third binary waveform based on the fourth binary waveform.

Claims

1. An apparatus comprising:

a fist unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform;

a second unanimity gate for generating a fourth binary waveform based on a second coincidence function of said first binary waveform and a fifth binary waveform; and

a fist temporal delay device for receiving said fourth binary waveform and for generating said third binary waveform based on said fourth binary waveform.

2. The apparatus of claim 1 wherein said first temporal delay device is a first bi-stable storage device.

3. The apparatus of claim 1 further comprising a second temporal delay device for generating a sixth binary waveform based on said first binary waveform.

4. The apparatus of claim 3 further comprising a third temporal delay device for receiving said third binary waveform and for generating a seventh binary waveform based on said third binary waveform.

5. The apparatus of claim 4 further comprising a third unanimity gate for generating an eighth binary waveform based on a third coincidence function of said sixth binary waveform and said seventh binary waveform.

6. The apparatus of claim 5 wherein said first coincidence functions said second coincidence function, and said third coincidence function are the same;

and

wherein said first timing signal and said second timing signal are out of phase with respect to each other.

7. An apparatus comprising:

a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform, a third binary waveform, and a fourth binary waveform;

a second unanimity gate for generating a fifth binary waveform based on a second coincidence function of said first binary waveform, said third binary waveform, and a sixth binary waveform; and

a third unanimity gate for generating a seventh binary waveform based on a third coincidence function of said first binary waveform, said fifth binary waveform, and an eighth binary waveform.

8. The apparatus of claim 7 further comprising:

a first temporal delay device for receiving said fifth binary waveform and for generating said fourth binary waveform based on said fifth binary waveform; and

a second temporal delay device for receiving said seventh binary waveform and for generating said third binary waveform based on said seventh binary waveform.

9. The apparatus of claim 7 further comprising:

a first bi-stable storage device for receiving said fifth binary waveform and a first timing signal, and for generating said fourth binary waveform based on said fifth binary waveform and said first timing signal; and

a second bi-stable storage device for receiving said seventh binary waveform and said first timing signal, and for generating said third binary waveform based on said seventh binary waveform and said first timing signal.

10. The apparatus of claim 8 further comprising:

a third bi-stable storage device for receiving said fourth binary waveform and a second timing signal and for generating a ninth binary waveform based on said fourth binary waveform and said second timing signal; and

a fourth bi-stable storage device for receiving said third binary waveform and a third timing reference signal and for generating a tenth binary waveform based on said third binary waveform and said third timing reference signal.

11. The apparatus of claim 10 further comprising a fourth unanimity gate for generating an eleventh binary waveform based on a fourth coincidence function of said twelfth bin waveform, said ninth binary waveform, and said tenth binary waveform.

12. The apparatus of claim 11 wherein said first coincidence function, said second coincidence function, said third coincidence function, and said fourth coincidence function are the same;

and

wherein said first timing signal, said second timing signal, and said third timing signal are out of phase with respect to each other.

13. An integrated circuit comprising:

a plurality of single-channel serializers, wherein each of said single-channel serializers comprises;

(i) a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform;

(ii) a second unanimity gate for generating a fourth binary waveform based on a second coincidence function of said first binary waveform and a fifth binary waveform; and

(iii) a first temporal delay device for receiving said fourth binary waveform and for generating said third binary waveform based on said fourth binary waveform.

14. The integrated circuit of claim 13 wherein said first temporal delay device is a first bi-stable storage device.

15. The integrated circuit of claim 13 wherein each of said single-channel serializers further comprises (iv) a second temporal delay device for receiving said first binary waveform and for generating a sixth binary waveform based on said first binary waveform.

16. The integrated circuit of claim 15 wherein each of said single-channel serializers further comprises (v) a third temporal delay device for receiving said third binary waveform and for generating a seventh binary waveform based on said third binary waveform.

17. The integrated circuit of claim 16 wherein each of said single-channel serializers further comprises (vi) a third unanimity gate for generating an eighth binary waveform based on a third coincidence function of said sixth binary waveform and said seventh binary waveform.

18. The integrated circuit of claim 17 wherein said first coincidence function, said second coincidence function, and said third coincidence function are the same.

19. An integrated circuit comprising:

a plurality of single-channel serializers, wherein each of said single-channel serializers comprises;

(i) a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform, a third binary waveform, and a fourth binary waveform;

(ii) a second unanimity gate for generating a fifth binary waveform based on a second coincidence function of said first binary waveform, said third binary waveform, and a sixth binary waveform; and

(iii) a third unanimity gate for generating a seventh binary waveform based on a third coincidence function of said first binary waveform, said fifth binary waveform, and an eighth binary waveform.

20. The integrated circuit of claim 19 wherein each of said single-channel serializers further comprises:

(iv) a first temporal delay device for receiving said fifth binary waveform and for generating said fourth binary waveform based on said fifth binary waveform; and

(v) a second temporal delay device for receiving said seventh binary waveform and for generating said third binary waveform based on said seventh binary waveform.

21. The integrated circuit of claim 19 wherein each of said single-channel serializers further comprises:

(iv) a first bi-stable storage device for receiving said fifth binary waveform and a first timing signal and for generating said fourth binary waveform based on said fifth binary waveform and said first timing signal; and

(v) a second bi-stable storage device for receiving said seventh binary waveform and said first timing signal and for generating said third binary waveform based on said seventh binary waveform and said first timing signal.

22. The integrated circuit of claim 20 wherein each of said single-channel serializers further comprises:

(vi) a third bi-stable storage device for receiving said fourth binary waveform and a second timing signal and for generating a ninth binary waveform based on said fourth binary waveform and said second timing signal; and

(vii) a fourth bi-stable storage device for receiving said third binary waveform and a third timing reference signal and for generating a tenth binary waveform based on said third binary waveform and said third timing reference signal.

23. The integrated circuit of claim 22 wherein each of said single-channel serializers further comprises:

(viii) a fourth unanimity gate for generating an eleventh binary waveform based on a fourth coincidence function of said first binary waveform, said ninth binary waveform, and said tenth binary waveform.

24. The integrated circuit of claim 23 wherein said first coincidence function, said second coincidence function, said third coincidence function, and said fourth coincidence function are the same;

and

wherein said first timing signal, said second timing signal, and said third timing signal are out of phase with respect to each other.