Method of and apparatus for handling high bandwidth on-screen-display graphics data over a distributed IEEE 1394 network utilizing an isochronous data transmission format

• US 6,593,937 B2
• Filed: 02/17/1999
• Issued: 07/15/2003
• Est. Priority Date: 06/18/1998
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Eyer, Mark Kenneth, Smyers, Scott D., Ludtke, Harold Aaron
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Sajous, Wesner
• Application Number:
  US09/251,586
• Publication Number:
  US 20020089517A1
• Time in Patent Office: 1,609 Days
• Field of Search: 348/569, 348/563, 348/564, 348/565, 348/568, 348/567, 348/584, 348/552, 348/553, 348/468, 345/618, 345/629, 345/630, 345/636, 345/714, 345/716, 345/717, 345/719, 345/534, 345/537, 345/538, 345/543, 345/545, 345/547, 345/555, 345/556, 345/564, 345/565, 345/567, 345/568, 345/572, 345/574, 710/62, 710/107, 709/232, 709/249, 709/250, 375/260
• US Class Current: 345/629
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1446 display composed of modules, e.g. video walls
• CPC Class Codes: G06T 15/10 Geometric effects
• CPC Class Codes: G09G 2300/026 Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04L 12/2805 Home Audio Video Interoperability [HAVI] networks
• CPC Class Codes: H04L 12/2834 Switching of information between an external network and a home network access arrangements H04L12/2856
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40071 Packet processing; Packet format adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/40117 Interconnection of audio or video/imaging devices home automation networks H04L12/2803; bitstream network arrangements specially adapted for distribution of digital video signals H04N7/24
• CPC Class Codes: H04L 2012/2849 Audio/video appliances
• CPC Class Codes: H04N 21/4135 external recorder interface circuits between an apparatus for recording television signals and a television receiver H04N5/775
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/43615 Interfacing a Home Network, e.g. for connecting the client to a plurality of peripherals home Audio Video Interoperability [HAVI] data switching networks H04L12/2805
• CPC Class Codes: H04N 21/43632 involving a wired protocol, e.g. IEEE 1394 high-speed IEEE 1394 serial bus H04L12/40052
• CPC Class Codes: H04N 5/262 Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
• CPC Class Codes: H04N 5/445 : for displaying additional information H04N5/50 takes precedence

Abstract

On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics. The trigger packet includes a presentation time value corresponding to a display time for the screen of on-screen-display graphics. When the trigger packet is received, the display device transfers the data stored in the buffer to a VRAM circuit for display at the specified presentation time. The on-screen-display graphics data can be overlaid on video data for display and also displayed separately. Differential encoding is used when transferring frames of data wherein only a portion of data changes from the previous frame.

Claims

1. A method of transmitting on-screen-display graphics data from a source device to a display device separate from a video stream of data comprising:

a. generating on-screen-display graphics to be displayed on the display device;

b. combining the on-screen-display graphics into a stream of data packets, each including an address value corresponding to a memory location within the display device; and

c. transmitting the data packets from the source device to the display device separate from the video stream of data.

2. The method as claimed in claim 1 further comprising transmitting a trigger packet on occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device.

3. The method as claimed in claim 2 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.

4. The method as claimed in claim 3 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.

5. The method as claimed in claim 1 wherein the data packets are isochronous packets.

6. The method as claimed in claim 1 wherein the data packets are asynchronous packets.

7. A method of transmitting on-screen-display graphics data from a source device to a display device comprising:

a. generating on-screen-display graphics to be displayed on the display device;

b. combining the on-screen-display graphics into a stream of isochronous data packets, each including an address value corresponding to a memory location within the display device;

c. transmitting the isochronous data packets from the source device to the display device over an isochronous channel; and

d. transmitting a trigger packet on the occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device.

8. The method as claimed in claim 7 further comprising:

a. receiving the isochronous data packets at the display device; and

b. storing data included within each of the isochronous data packets at the memory location specified by the address value included within the isochronous data packet.

9. The method as claimed in claim 8 further comprising:

a. compressing the on-screen-display graphics before the isochronous data packets are formed; and

b. decompressing the data at the display device before the storing is completed.

10. The method as claimed in claim 7 wherein the trigger packet further includes a presentation time value specifying a display time for the on-screen-display graphics.

11. The method as claimed in claim 10 wherein the trigger event occurs when all isochronous data packets for a screen of the on-screen-display graphics have been transmitted.

12. The method as claimed in claim 11 further comprising:

a. receiving the isochronous data packets at the display device;

b. storing data included within each of the isochronous data packets at the memory location specified by the address value included within the isochronous data packet;

c. receiving the trigger packet at the display device;

d. storing the trigger packet at the trigger memory location; and

e. displaying the screen of on-screen-display graphics at the display time.

13. The method as claimed in claim 12 wherein the memory locations and the trigger memory location within the display device are included within an on-screen-display graphics buffer.

14. The method as claimed in claim 13 wherein the memory locations are included within an on-screen-display graphics buffer and the trigger memory location is included within a trigger buffer.

15. The method as claimed in claim 13 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.

16. The method as claimed in claim 15 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.

17. The method as claimed in claim 13 wherein the isochronous data packets and the trigger packet are transmitted from the source device to the display device over a high speed serial interface.

18. The method as claimed in claim 17 wherein the high speed serial interface is an IEEE 1394 serial bus network.

19. The method as claimed in claim 11 further comprising:

a. generating a subsequent screen of on-screen-display graphics to be displayed on the display device;

b. determining changed pixels within the subsequent screen as compared to a previous screen of on-screen-display graphics;

c. combining the on-screen-display data representing only the changed pixels into a differential stream of isochronous data packets, each differential isochronous packet including an address value corresponding to the memory location related to represented changed pixels; and

d. transmitting the isochronous data packets from the source device to the display device over the isochronous channel.

20. A method of receiving on-screen-display graphics data, generated by a source device and transmitted in isochronous data packets over an isochronous channel to a display device, each isochronous data packet including an address value corresponding to a memory location within the display device, comprising:

a. receiving an isochronous data packet including on-screen-display graphics data and the address value;

b. storing the on-screen-display graphics data included within the isochronous data packet at the memory location within the display device;

c. receiving a trigger packet including a trigger address value, corresponding to a trigger memory location within the display device, and presentation time value specifying a display time for the on-screen-display graphics; and

d. displaying the on-screen-display graphics at the display time.

21. The method as claimed in claim 20 further comprising storing the trigger packet at the trigger memory location.

22. The method as claimed in claim 21 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.

23. The method as claimed in claim 21 further comprising decompressing the on-screen-display graphics, if the on-screen-display graphics had previously been compressed, before the storing is completed.

24. The method as claimed in claim 21 wherein the memory locations and the trigger memory location are included within an on-screen-display graphics buffer.

25. The method as claimed in claim 24 wherein the isochronous data packets and the trigger packet are transmitted from the source device to the display device over a high speed serial interface.

26. The method as claimed in claim 25 wherein the high speed serial interface is an IEEE 1394 serial bus network.

27. An apparatus for transmitting on-screen-display graphics data from a source device to a display device comprising:

a. a graphics source for generating on-screen-display graphics to be displayed by the display device;

b. an interface circuit coupled to the graphics source and configured for coupling to the display device for combining the on-screen-display graphics into a stream of isochronous data packets each including an address value corresponding to a memory location within the display device and transmitting the isochronous data packets from the source device to the display device over an isochronous channel;

wherein the graphics source also generates a trigger packet which is transmitted by the interface circuit on the occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device.

28. The apparatus as claimed in claim 27 wherein the trigger event occurs when all isochronous data packets for a screen of on-screen-display graphics have been transmitted from the interface circuit.

29. The apparatus as claimed in claim 28 wherein the trigger packet further includes a presentation time value specifying a display time for the screen of on-screen-display graphics.

30. The apparatus as claimed in claim 29 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.

31. The apparatus as claimed in claim 30 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.

32. The apparatus as claimed in claim 29 further comprising a compression circuit coupled to the graphics source and to the interface circuit for compressing the on-screen-display graphics before transmission by the interface circuit.

33. The apparatus as claimed in claim 32 wherein the interface circuit is coupled to the display device by a high speed serial interface.

34. The apparatus as claimed in claim 33 wherein the high speed serial interface is an IEEE 1394 serial bus network.

35. An apparatus for receiving on-screen-display graphics data generated by a source device and transmitted in isochronous data packets over an isochronous channel, each isochronous data packet including an address value corresponding to a memory location, comprising:

a. an interface circuit configured for coupling to the source device for receiving the isochronous data packets from the source device over the isochronous channel;

b. a processing device coupled to the interface circuit for receiving the isochronous data packets and separating the address value from the on-screen-display graphics data;

c. a memory device coupled to the processing device to store the on-screen-display graphics data in a memory location corresponding to the address value; and

d. a display device coupled to the memory device for displaying the on-screen-display graphics at a display time, wherein the display time is received in a trigger packet.

36. The apparatus as claimed in claim 35 wherein the processing device is an embedded stream processor which determines if on-screen-display graphics data is included within the isochronous data packets, strips header information from the isochronous data packets, determines the address value and transmits the address value and the on-screen-display graphics data to the memory device.

37. The apparatus as claimed in claim 36 wherein the memory device includes a buffer and a DMA engine which receives the address value and stores the on-screen-display graphics data in the memory location corresponding to the address value within the buffer.

38. The apparatus as claimed in claim 37 wherein the display device includes a display and a VRAM circuit in which the on-screen-display graphics are stored before being displayed on the display.

39. The apparatus as claimed in claim 38 wherein the interface circuit is coupled to the source device by a high speed serial interface.

40. The apparatus as claimed in claim 39 wherein the high speed serial interface is an IEEE 1394 serial bus network.

41. A system for transmitting on-screen-display graphics data comprising:

a. a source device including;

i. a graphics source for generating on-screen-display graphics to be displayed by a display device; and

ii. a source interface circuit coupled to the graphics source and configured for coupling to the display device for combining the on-screen-display graphics into a stream of isochronous data packets each including an address value corresponding to a memory location within the display device and transmitting the isochronous data packets from the source device to the display device over an isochronous channel; and

b. a display device including;

i. a display interface circuit coupled to the source interface circuit for receiving the isochronous data packets from the source device over the isochronous channel;

ii. a processing device coupled to the display interface circuit for receiving the isochronous data packets and separating the address value from the on-screen-display graphics data;

iii. a memory device coupled to the processing device to store the on-screen-display graphics data in a memory location corresponding to the address value; and

iv. a display device coupled to the memory device for displaying the on-screen-display graphics at a display time;

wherein the graphics source also generates a trigger packet which is transmitted by the interface circuit on the occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device.

42. The system as claimed in claim 41 wherein the trigger event occurs when all isochronous data packets for a screen of on-screen-display graphics have been transmitted from the source interface circuit.

43. The system as claimed in claim 42 wherein the trigger packet further includes a presentation time value specifying the display time for the screen of on-screen-display graphics.

44. The system as claimed in claim 43 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.

45. The system as claimed in claim 44 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.

46. The system as claimed in claim 41 wherein the processing device is an embedded stream processor which determines if on-screen-display graphics data is included within the isochronous data packets, strips header information from the isochronous data packets, determines the address value and transmits the address value and the on-screen-display graphics data to the memory device.

47. The system as claimed in claim 46 wherein the memory device includes a buffer and a DMA engine which receives the address value and stores the on-screen-display graphics data in the memory location corresponding to the address value within the buffer.

48. The system as claimed in claim 47 wherein the display device includes a display and a VRAM circuit in which the on-screen-display graphics are stored before being displayed on the display.

49. The system as claimed in claim 48 wherein the source interface circuit is coupled to the display interface circuit by a high speed serial interface.

50. The system as claimed in claim 49 wherein the high speed serial interface is an IEEE 1394 serial bus.