Wear leveling techniques for flash EEPROM systems

• US 6,594,183 B1
• Filed: 06/30/1998
• Issued: 07/15/2003
• Est. Priority Date: 09/13/1991
• Status: Expired due to Fees

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation), Western Digital Corporation
• Inventors: Gupta, Anil, Norman, Robert D., Lofgren, Karl M. J., Thelin, Gregory B.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/108,084
• Time in Patent Office: 1,841 Days
• Field of Search: 365/185.33, 365/182, 365/185.29, 365/185.09, 365/185.01, 365/185.03
• US Class Current: 365/185.33
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

Claims

1. A storage device employing a flash memory, wherein a storage area of said storage device is divided into a plurality of physical sectors identified by physical addresses, said storage device includes:

logical address conversion means which receives a logical address of data in a data writing operation and converts said logical address into a physical address,

a memory controller for receiving said physical address resulting from the conversion by the conversion means, and writing said data into a respective physical sector;

wherein said logical address conversion means converts a logical address received in the writing operation to the physical address which is different from the physical address to which said logical address conversion means converted a logical address, identical to the logical address to be presently converted, in a preceding writing operation,

erase operations reference means for storing a number of erase operations of respective erasing sector groups each of which comprises one or more physical sectors erased together in one erasing operation when erasing data stored in the physical sector included in the erasing sector groups, and

erasing control means for erasing the erasing sector groups in the erasing operations, referring to said erase operations reference means, in which the number of erasing operations performed by the erasing sector groups are averaged.

2. In a memory system including non-volatile erasable and re-programmable memory cells characterized by experiencing degradation as a number of erase and re-programming cycles increases, a method of programming data received external of the memory system, comprising:

utilizing the memory cells divided into a plurality of groups that individually includes one or more units of memory cells that are erasable together,

receiving a first unit of data and a first logical address therefore from outside the memory system,

converting the received first logical address into a first physical memory address of a first erase unit,

programming data of the received first unit of data into memory cells of the first erase unit,

subsequently receiving a second unit of data and the first logical address therefore from the host system,

thereafter converting the received first logical address into a second physical memory address of a second erase unit that is within a different group of memory cells than the first erase unit and is chosen to tend to even out the number of erase and re-programming cycles experienced by the groups of memory cells, and

programming the received second unit of data into memory cells of the second erase unit.

3. The method of claim 2, which additionally comprises, after programming the received second unit of data, erasing the memory cells of the first erase unit, whereby the first erase unit thereafter becomes available to have other data programmed therein.

4. The method of claim 2, wherein utilizing the memory cells includes utilizing the groups including the first and second units of memory cells on different integrated circuit chips.

5. The method of claim 2 that additionally comprises maintaining an indication related to a number of erase and re-programming cycles experienced by the individual groups of one or more erase units of memory cells, and wherein converting the received first logical address into the second physical memory address includes choosing the group of memory cells containing the second erase unit by reference to at least the indication related to the number of erase and programming cycles experienced by the group including the second erase unit.

6. The method of claim 5, wherein utilizing the memory cells includes utilizing the groups including the first and second units of memory cells on different integrated circuit chips.

7. The method of claim 5, wherein utilizing the memory cells divided into groups includes only one erase unit of memory cells in individual ones of the groups.

8. The method of claim 5, wherein utilizing the memory cells divided into groups includes a plurality of erase units of memory cells in individual ones of the groups.

9. The method of claim 5, wherein utilizing the memory cells includes limiting the number of erase and re-programming cycles that the memory cells are allowed to endure to a specified number, and wherein converting the received first logical address into the second physical memory address includes doing so prior to the erase and re-programming cycles of either of the first or second erase units reaching the specified number.

10. The method of claim 5, wherein the first and second units of data and the first and second logical addresses are received from a host system to which the memory system is operably connected.

11. The method of claim 2, wherein utilizing the memory cells divided into a plurality of groups includes utilizing only one erase unit of memory cells in individual ones of the groups.

12. The method of claim 2, wherein utilizing the memory cells divided into groups includes a plurality of erase units of memory cells in individual ones of the groups.

13. The method of claim 2, wherein utilizing the memory cells includes limiting the number of erase and re-programming cycles that the memory cells are allowed to endure to a specified number, and wherein converting the received first logical address into the second physical memory address includes doing so prior to the erase and re-programming cycles of either of the first or second units reaching the specified number.

14. The method of claim 2, wherein the first and second units of data and the first and second logical addresses are received from a host system to which the memory system is operably connected.

15. A method of operating a memory system including non-volatile erasable and re-programmable memory cells with a target endurance limit of a maximum number of erase and re-programming cycles to which the memory cells are to be subjected, comprising:

utilizing the memory cells divided into a plurality of units of memory cells that are erasable together,

receiving a unit of data and a logical address of a memory cell erase unit therefore from a host system,

temporarily storing the received unit of data in a buffer memory,

converting the received logical address into a physical address of one of the plurality of memory cell erase units that tends to even out the frequency of use of the memory cell erase units prior to any such erase unit reaching the target maximum number of erase and re-programming cycles, and

thereafter programming the received unit of data from the buffer memory into said one of the plurality of memory cell erase units.

16. The method of claim 15, wherein utilizing the memory cells divided into a plurality of erase units of memory cells includes utilizing a plurality of said units of memory cells that are erasable together on a plurality of integrated circuit chips.

17. The method of claim 15, wherein converting the received logical address includes utilizing a measure of a degree of unevenness in the usage of the plurality of memory cell erase units in order to select said physical address of one of the memory cell erase units.

18. The method of claim 17, wherein converting the received logical address includes measuring a degree of unevenness in the usage of the plurality of memory cell erase units by comparing a difference between a lowest used erase unit and a highest used erase unit with a predetermined difference number.

19. The method of claim 17, wherein converting the received logical address includes measuring a degree of unevenness in the usage of the plurality of memory cell erase units by averaging usage of a plurality of memory cell erase units.