Write-inhibit circuit, semiconductor integrated circuit using the same, ink cartridge including the semiconductor integrated circuit, and ink-jet recording apparatus

• US 6,594,185 B1
• Filed: 07/26/2001
• Issued: 07/15/2003
• Est. Priority Date: 10/04/1999
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Takagi, Tetsuo
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/857,471
• Time in Patent Office: 719 Days
• Field of Search: 365/195, 365/189.01, 365/189.08, 365/196, 365/207
• US Class Current: 365/189.15
• CPC Class Codes: B41J 2/17546 electronically
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

Chip area and operating current is reduced in a chip having a write-inhibit circuit that uses a data-writing request signal WR and a write-control signal WRITE to inhibit data writing. By comparing a reference current Iref and a drive current ID, a current-mirror circuit CM can monitor the voltage of a power supply VDD. When the voltage of the power supply VDD is sufficiently high, the data-writing request signal WR is unchanged. Conversely, when the voltage of the power supply VDD is not sufficiently high, a transistor T6 producing reference-current I_D and a buffer B2 cause the write-control signal to be low “L” irrespective of whether the data-writing request signal WR is at “H” or at “L”. Thus, miswriting can be prevented when the power-supply voltage decreases, since writing by the data-writing request signal WR is impossible.

Claims

1. A write-inhibit circuit comprising:

an input node for receiving a data-writing request signal;

an output node for outputting an output write-control signal to inhibit data writing;

a current mirror circuit having a first transistor array in parallel with a second transistor array between a high potential power supply and a low potential power supply, said first transistor array including a first plurality of series-connected transistors including a depletion transistor for generating a reference-current, said second transistor array including a second plurality of transistors and being effective for producing a signal current in response to the data-writing request signal received at said input node;

wherein the write-inhibit circuit is effective for providing an output signal at said output node indicative of a comparison between said reference current and said signal current when the voltage of said high potential power supply is not lower than a predetermined value, and when the voltage of said high potential power supply decreases below said predetermine value, the write-inhibit circuit is effective for providing a second output signal at said output node determined only by said reference current.

2. A write-inhibit circuit as set forth in claim 1, wherein:

the second transistor array is formed by connecting in series a first transistor which is connected to the high potential power supply and which is switched on in accordance with the data-writing request signal, a second transistor which allows a current equal to that flowing via the first transistor to flow in the first transistor array, and a third transistor which is switched on together with the first transistor and which forms a current path to the low potential power supply;

the first transistor array is formed by connecting in series a fourth transistor which is connected to the high potential power supply and which is switched on in accordance with the data-writing request signal, a fifth transistor having a gate electrode connected in common to the gate terminal of the second transistor, and a sixth transistor as the depletion transistor; and

the write-control signal is output from the junction of the fifth transistor and the sixth transistor.

3. A semiconductor integrated circuit including:

a write-inhibit circuit as set forth in claim 1;

a memory store of memory cells for storing data at a designated address; and

an address generating circuit for sequentially generating addresses for designation in the memory store;

wherein the writing of the data in the memory store is inhibited based on said write-control signal output from the write-inhibit circuit.

4. A semiconductor integrated circuit as set forth in claim 3, further including control means for performing control so as to perform transfer to a low power consumption mode having power consumption less than a normal operating mode for performing a normal operation, wherein the semiconductor integrated circuit is provided in an ink cartridge, and performs transfer to the low power consumption mode in response to the termination of a printing operation using the ink cartridge.

5. A semiconductor integrated circuit as set forth in claim 4, wherein the address is initialized when the control means performs transfer to the low power consumption mode.

6. A semiconductor integrated circuit as set forth in claim 5, wherein in the low power consumption mode activated by the control means, the operation of an internal circuit is terminated.

7. A semiconductor integrated circuit as set forth in claim 6, wherein the internal circuit is a sense amplifier for generating a signal in response to reading data stored in the memory store.

8. A semiconductor integrated circuit as set forth in claim 6, wherein the internal circuit is an address decoder for designating an address in the memory store.

9. A semiconductor integrated circuit as set forth in claim 6, wherein the internal circuit is a buffer used when data is read from the memory store.

10. A semiconductor integrated circuit as set forth in claim 6, wherein the internal circuit is a latch circuit for latching data read from the memory store.

11. A semiconductor integrated circuit as set forth in claim 4, wherein implementation of the transfer to the low power consumption mode and the initialization of the address generated by the address generating circuit is based on a control signal input to a common external terminal.

12. A semiconductor integrated circuit as set forth in claim 11, wherein the common external terminal is a chip-select terminal.

13. An ink cartridge including a semiconductor integrated circuit as set forth in claim 3, wherein a value of the remaining amount of ink in said ink cartridge is stored in said memory store.

14. An ink-jet recording apparatus having an ink cartridge as set forth in claim 13, wherein the ink-jet recording apparatus uses ink supplied from the ink cartridge to print image information.