PWM power amplifier with digital input

• US 6,594,309 B1
• Filed: 02/03/2000
• Issued: 07/15/2003
• Est. Priority Date: 02/11/1999
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Botti, Edoardo, Grosso, Antonio
• Primary Examiner(s): Vo, Don N.
• Application Number:
  US09/497,843
• Time in Patent Office: 1,258 Days
• Field of Search: 375/238, 375/242, 329/312, 332/109, 330/10, 330/251, 330/262, 341/126, 341/144
• US Class Current: 375/238
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/825 by comparing the input signal with a digital ramp signal

Abstract

A digital input PWM power amplifier includes an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number of M bits at a bit rate, and outputting PCM digital data organized in words of a smaller number of N bits at a multiple bit rate. A first bus transmits a first number of most significant bits (MSB) of the N bit words output from the oversampling and noise shaping circuit, and a second bus transmits a second number of least significant bits (LSB) of the N bit words output from the oversampling and noise shaping circuit. First and second PCM/PWM converters are respectively fed with the first and second number of bits transmitted through the first and second buses. The PWM signal output by the first converter is summed to an attenuated PWM signal output by the second converter on the inverting input node of the output power stage.

Claims

1. A digital input PWM power amplifier comprising:

an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number of M bits at a bit rate, and outputting PCM digital data organized in words of a smaller number of N bits at a multiple of the bit rate;

a first bus transmitting a first number of most significant bits (MSBs) of the N bit words output from said oversampling and noise shaping circuit, and a second bus transmitting a second number of least significant bits (LSBs) of the N bit words output from said oversampling and noise shaping circuit;

first and second PCM/PWM converters respectively fed from said first and second buses, each PCM/PWM converter comprising

a counter driven by a clock signal having a frequency equal to the product of the bit rate of the MSBs or LSBs transmitted on the respective buses times the base two raised to the respective first or second number of MSBs and LSBs for generating reference digital words and defining ramps of digital values with a frequency equal to a frequency of the multiple of the bit rate, and

a digital comparator receiving through a first input the reference digital words and through a second input the respective first or second number of MSBs and LSBs, and outputting a respective PWM signal; and

an output power stage having an inverting input receiving a driving signal defined by a PWM signal output by said first PCM/PWM converter summed with an attenuated PWM signal output by said second PCM/PWM converter.

2. A PWM power amplifier according to claim 1, wherein each of said first and second PCM/PWM converters comprises a single ramp converter.

3. A PWM power amplifier according to claim 1, wherein each of said first and second PCM/PWM converters comprises a double ramp converter;

and each of said counters comprises an up/down counter for generating reference digital words in a form of rising and falling ramps in succession at half a frequency of the multiple of the bit rate.

4. A PWM power amplifier according to claim 1, wherein said output power stage comprises a single output power stage which is single ended.

5. A PWM power amplifier according to claim 1, wherein said output power stage comprises a pair of output power stages functioning in phase opposition in which an inversion of the driving signal to an inverting input of one of said pair of power stages is formed by inverting the PWM signals output by said first and second PCM/PWM converters.

6. A PWM power amplifier according to claim 1, wherein each of said first and second PCM/PWM converters comprises a pair of PCM/PWM converter circuits respectively connected to said first and second buses, and one of said pair of PCM/PWM converter circuits respectively receives an inversion of the first or second number of MSBs and LSBs transmitted through said first and second buses;

and wherein said output power stage comprises a pair of output power stages functioning in phase opposition and in which an inversion of the driving signal of one of said pair of output power stages is formed by the pair of PCM/PWM converter circuits receiving the inversion of the first and second number of MSBs and LSBs transmitted by said first and second buses.

7. A PWM power amplifier according to claim 1, wherein each of said first and second PCM/PWM converters comprises a pair of PCM/PWM converter circuits respectively connected to said first and second buses, and one of said pair of PCM/PWM converter circuits receives inverted ramp inversion commands;

and wherein said output power stage comprises a pair of output power stages functioning in phase opposition such that one of said output power stages is connected to the pair of PCM/PWM converter circuits receiving the inverted ramp inversion commands.

8. A PWM power amplifier according to claim 7, further comprising:

an invertor for inverting the respective PWM signals output by said PCM/PWM converter circuits receiving the LSBs;

an attenuator for attenuating the inverted PWM signals; and

an adder circuit to respectively sum the attenuated inverted PWM signals with the driving signal produced by said pair of PCM/PWM converter circuits not providing the inverted PWM signals to be summed therewith.

9. A digital input PWM power amplifier comprising:

an input circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number of M bits at a bit rate, and outputting PCM digital data organized in words of a smaller number of N bits at a multiple of the bit rate;

a first bus transmitting a first number of most significant bits (MSBs) of the N bit words output from said input circuit, and a second bus transmitting a second number of least significant bits (LSBs) of the N bit words output from said input circuit;

first and second converters respectively fed from said first and second buses, each converter comprising

a counter driven by a clock signal having a frequency equal to the product of the bit rate of the MSBs or LSBs transmitted on the respective buses times the base two raised to the respective first or second number of MSBs and LSBs, and

a digital comparator receiving through a first input the reference digital words and through a second input the respective first or second number of MSBs and LSBs, and outputting a respective PWM signal; and

an output power stage having an input receiving a driving signal defined by a PWM signal output by said first converter summed with an attenuated PWM signal output by said second converter.

10. A PWM power amplifier according to claim 9, wherein said input circuit comprises an oversampling and noise shaping circuit.

11. A PWM power amplifier according to claim 9, wherein each converter comprises a PCM/PWM converter.

12. A PWM power amplifier according to claim 9, wherein each converter defines ramps of digital values with a frequency equal to a frequency of the multiple of the bit rate.

13. A PWM power amplifier according to claim 9, wherein the input of said output power stage receiving the driving signal is an inverted input.

14. A PWM power amplifier according to claim 9, wherein each of said first and second PCM/PWM converters comprises a single ramp converter.

15. A PWM power amplifier according to claim 9, wherein each of said first and second converters comprises a double ramp converter;

and each of said counters comprises an up/down counter for generating reference digital words in a form of rising and falling ramps in succession at half a frequency of the multiple of the bit rate.

16. A PWM power amplifier according to claim 9, wherein said output power stage comprises a single output power stage which is single ended.

17. A PWM power amplifier according to claim 9, wherein said output power stage comprises a pair of output power stages functioning in phase opposition in which an inversion of the driving signal to an inverting input of one of said pair of power stages is formed by inverting the PWM signals output by said first and second converters.

18. A PWM power amplifier according to claim 9, wherein each of said first and second converters comprises a pair of converter circuits respectively connected to said first and second buses, and one of said pair of converter circuits respectively receives an inversion of the first or second number of MSBs and LSBs transmitted through said first and second buses;

and wherein said output power stage comprises a pair of output power stages functioning in phase opposition and in which an inversion of the driving signal of one of said pair of output power stages is formed by the pair of converter circuits receiving the inversion of the first and second number of MSBs and LSBs transmitted by said first and second buses.

19. A PWM power amplifier according to claim 9, wherein each of said first and second converters comprises a pair of converter circuits respectively connected to said first and second buses, and one of said pair of converter circuits receives inverted ramp inversion commands;

and wherein said output power stage comprises a pair of output power stages functioning in phase opposition such that one of said output power stages is connected to the pair of converter circuits receiving the inverted ramp inversion commands.

20. A PWM power amplifier according to claim 19, further comprising:

an invertor for inverting the respective PWM signals output by said converter circuits receiving the LSBs;

an attenuator for attenuating the inverted PWM signals; and

an adder circuit to respectively sum the attenuated inverted PWM signals with the driving signal produced by said pair of converter circuits not providing the inverted PWM signals to be summed therewith.

21. A method for converting a PCM signal to a PWM signal for a PWM power amplifier comprising the steps of:

dividing the PCM signal comprising words of a first number of M bits at a bit rate into words of a smaller number of N bits at a multiple of the bit rate;

transmitting a first number of most significant bits (MSBs) of the N bit words on a first bus, and transmitting a second number of least significant bits (LSBs) of the N bit words on a second bus;

driving a pair of counters by respective clock signals having a frequency equal to the product of the bit rate of the MSBs or LSBs transmitted on the respective buses times the base two raised to the respective first and second number of bits for generating reference digital words; and

generating a driving signal based upon the pair of counter.

22. A method according to claim 21, wherein the step of generating comprises:

comparing the respective reference digital words with the respective first and second number of bits for outputting a respective PWM signal; and

summing a PWM signal with an attenuated PWM signal output defining the driving signal.

23. A method according to claim 21, wherein the step of driving the pair of counters comprises respectively defining ramps of digital values with a frequency equal to a frequency of the multiple of the bit rate.

24. A method according to claim 23, wherein the ramps are single ramps.

25. A method according to claim 21, wherein the driving signal is applied to an output power stage of the PWM power amplifier.

26. A method according to claim 24, wherein the ramps are double ramps;

and the pair of counters comprise up/down counters for generating reference digital words in a form of rising and falling ramps in succession at half a frequency of the multiple of the bit rate.

27. A method according to claim 21, wherein the driving signal is applied to a pair of output power stages of the PWM power amplifier, the pair of output power stages functioning in phase opposition in which an inversion of the driving signal applied to an inverting input of one of the pair of power stages is formed by inverting the respective PWM signals.

28. A method according to claim 21, wherein each counter comprises a pair of counter circuits respectively connected to the first and second buses, and one of the pair of counters receives an inversion of the first and second number of bits transmitted through the first and second buses;

and wherein the driving signal is applied to a pair of output power stages of the PWM power amplifier, the pair of output power stages functioning in phase opposition and in which an inversion of the driving signal of one of the pair of output power stages is formed by the counter circuits receiving the inversion of the first and second number of MSBs and LSBs bits transmitted through the first and second buses.