Method for unique determination of FET equivalent circuit model parameters

• US 6,594,594 B1
• Filed: 10/05/2000
• Issued: 07/15/2003
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Tsai, Roger Su-Tsung
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Desta, Elias
• Application Number:
  US09/680,339
• Time in Patent Office: 1,013 Days
• Field of Search: 702/1, 702/57, 702/64, 702/65, 702/66, 702/69, 702/79, 702/108, 702/117, 702/119, 702/120, 702/123, 702/124, 702/182, 702/183, 702/189, 324/600, 324/60, 324/629, 324/649, 324/658, 324/661, 324/691, 324/722, 324/726, 716/1-4, 716/8, 716/489
• US Class Current: 702/65
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method of uniquely extracting both intrinsic and parasitic components from a single set of measured S-parameters is useful for extracting a single set of measured S-parameters for the development of non-linear Field Effect Transistor (FET) models. Competitive extraction where multiple trial solutions are attempted spanning a region or space of feedback impedances is used. Extraction is followed by optimization that reduces the extracted values to a model that better fits measured S-parameters. Optimization can be achieved by further evaluating the speed of convergence in an error metric.

Claims

1. A method of generating a set of equivalent circuit parameter values for a FET device comprising the steps of:

measuring a set of S-parameter values associated with the FET device;

generating a circuit model of the FET device;

defining trial Impedance points for the FET circuit model;

extracting model S-parameter values for each trial impedance point for the FET circuit model;

calculating modeled S-parameters from the extracted model parameters for the circuit model for each trial impedance point;

comparing the modeled S-parameters to the measured S-parameters for each trial impedance point;

optimizing the modeled S-parameter values for each trial impedance point by applying a preselected computational resource controlled optimization criteria to each trial impedance point;

calculating an error fit between the optimized S-parameter values and the measured S-parameter values for each trial impedance point; and

,

determining a set of equivalent circuit parameters for the FET device by selecting the trial impedance point and model parameter values which resulted in a minimum error fit.

2. The method of claim 1, further comprises repeating the extracting, calculating modeled S-parameters and comparing steps until the preselected criteria is met for each trial impedance point.

3. The method of claim 2, wherein applying a preselected criteria comprises applying a preselected number of times the extracting model S-parameter values, calculating model S-parameter values and comparing model S-parameter values steps are conducted for each trial impedance point.

4. The method of claim 1, wherein extracting model parameters comprises extracting model parameters using a Minasian extraction technique.

5. The method of claim 1, wherein extracting model parameters comprises fixing a value of one model parameter and using a Minasian extraction technique to extract other model parameters.

22. The method according to claim 1, wherein said step of optimizing comprises optimizing the modeled S-parameter values for each trial impedance point by applying a preselected computational time limiting criteria to each trial impedance point.

23. The method according to claim 1, wherein said step of optimizing comprises optimizing the modeled S-parameter values for each trial impedance point by applying a preselected computational resource limited criteria to each trial impedance point which comprises fixing constant the number of numeric optimization cycles to each trial impedance point to minimize the error fit between the modeled and the measured S-parameters.

6. A method of generating a set of unique device equivalent circuit parameter values that closely model measured S-parameters for a FET-type device comprising the steps of:

generating a circuit model of the FET-type device;

measuring a set of S-parameters associated with the FET-type device;

extracting equivalent circuit model parameter values associated with the FET-type device, for a fixed value of feedback impedance, representing a trial solution lying in a space containing a set of feedback impedance trial values;

modeling the S-parameters by applying the equivalent circuit model parameters to the circuit model;

determining an error fit between the modeled S-parameters to the measured S-parameters;

optimizing the extracted equivalent circuit parameter values by applying a preselected computational resource limited criteria to each trial impedance point to minimize the error fit between the modeled and the measured S-parameters; and

deriving a set of unique equivalent circuit parameters for the device by evaluating the error fit between said set of modeled S-parameters and said set of measured S-parameters, wherein the trial impedance point which converges quickest for said preselected criteria is the trial impedance point that minimizes the error fit.

7. The method according to claim 6 further comprising the step of selecting a set of model parameter values with a minimal error fit between said modeled S-parameters and said measured S-parameters.

8. The method according to claim 6 further comprising the step of generating a space of feedback impedance values for use during said determining step.

9. The method according to claim 6 wherein the step of measuring is followed by the further step of storing said set of parameters associated with the device.

10. The method according to claim 6 further comprising the step of determining if the measured set of S-parameters is confined within a known space of expected S-parameters.

11. The method according to claim 6 wherein the step of optimizing comprises applying multiple trial solutions spanning a known space of expected values to optimize the modeled S-parameters for each trial impedance point.

12. The method according to claim 6 wherein the step of extracting comprises applying Minasian extraction techniques to arrive at model parameter values for said FET device.

13. The method according to claim 6 wherein the step of determining an error fit comprises determining a speed of convergence for each trial impedance point, and, the step of deriving comprises deriving a set of unique equivalent circuit parameters for the FET device by evaluating the speed of convergence for each trial impedance point.

14. The method according to claim 6 further comprising the step of creating an error metric for a set of points with a known space of parameter values.

15. The method according to claim 6 wherein said step of deriving is performed utilizing extracted parameter values that converge fastest to measured S-parameters.

24. The method according to claim 6, wherein said step of optimizing comprises optimizing the extracted equivalent circuit parameter values by applying a preselected computational time limiting criteria to each trial impedance point to minimize the error fit between the modeled and the measured S-parameters.

25. The method according to claim 6, wherein said step of optimizing comprises optimizing the extracted equivalent circuit parameter values by applying a preselected computational resource limited criteria which comprises fixing constant the number of numeric optimization cycles to each trial impedance point to minimize the error fit between the modeled and the measured S-parameters.

16. A method for unique determination of FET equivalent circuit parameters comprising the steps of:

generating a set of feedback impedance values that define a space of expected parameter values;

generating a FET equivalent circuit model;

applying the feedback impedance values to the circuit model and calculating therefrom modeled S-parameters for each feedback impedance value;

measuring a set of S-parameters from the actual FET;

comparing the measured S-parameter to the modeled S-parameters; and

selecting the S-parameter values for the circuit model that converge so that a sufficiently low error fit between the modeled S-parameters and the measured S-parameters is obtained, said convergence obtained using multiple Minasian extraction cycles.

17. The method according to claim 16 wherein said step of selecting is performed so that the selected parameters contains values associated with the fastest convergence between the measured S-parameters and the modeled S-parameters.

18. The method according to claim 16 further comprising the step of storing said measured S-parameters.

19. The method according to claim 16 further comprising the step of creating an error metric based on the error fit between the modeled S-parameters and the measured S-parameters and the speed of convergence.

20. The method according to claim 16 wherein said step of selecting the unique parameters includes selecting resistive, capacitive and inductive equivalent circuit parameters for said FET equivalent circuit model.

21. The method according to claim 20 wherein said step of selecting includes selecting equivalent circuit parameters that represent the physical structure of a device based on said FET equivalent circuit model.