Reconfigurable FIFO interface to support multiple channels in bundled agent configurations

• US 6,594,714 B1
• Filed: 05/01/2000
• Issued: 07/15/2003
• Est. Priority Date: 05/01/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Jones, Jason, Sharma, Debendra Das, Swanson, Jeffrey C.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): PATEL, NIKETA I
• Application Number:
  US09/561,953
• Time in Patent Office: 1,170 Days
• Field of Search: 710/1, 710/36, 710/70, 710/128, 710/38, 710/51, 711/127, 714/738, 370/200
• US Class Current: 710/51
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

A reconfigurable register array structure allows an agent to transmit data from a single channel or in bundled form from multiple channels. The structure makes economical use of valuable chip space by reducing the size of the overall register array system. A coalescing prestage is used to collect data from single channels or from multiple channels and to multiplex the data, based on a priority scheme, to supply the data to a primary stage of first-in-first-out register arrays. The coalescing prestage may include one or more first registers, a delay register, multiplexers to select outputs of the first registers, and multiplexers to select outputs of the delay register. Alternatively, the coalescing prestage may include one or more register array structures, each such structure having independent write ports, one for each channel. Data coalesced in the coalescing prestage is provided to a primary stage. The primary stage may include one or more logical register arrays configured as one physical array. Separate write pointers may be used to ensure data from a particular channel is provided to the correct location in the physical array.

Claims

1. An reconfigurable first-in/first-out mechanism to support multiple channels in a bundled agent configuration, comprising:

a coalescing prestage comprising;

first registers, each of the first registers capable of holding X data bits, each of the first registers receiving data bits in increments of X/N, where N is an integer, and wherein each of the first registers coalesces the X/N data bits until X data bits are stored, and

second registers, each of the second registers capable of holding at least X/N data bits, the second registers coupled to selected ones of the first registers, wherein the second registers store the at least X/N data bits to impose a delay in transferring the X/N data bits to the selected ones of first registers; and

a bundled first-in-first out (FIFO) stage coupled to the coalescing prestage.

2. The mechanism of claim 1, the coalescing prestage further comprising a first multiplexer coupled between each of the selected ones of the first registers and one of the second registers, wherein the first multiplexer operates to select either an output of the one of the second registers and a data bit input of X/N data bits.

3. The mechanism of claim 1, the coalescing prestage further comprising second multiplexers, each of the second multiplexers coupled to an output of one or more of the first registers, wherein a second multiplexer selects an output from one of the coupled one or more first registers, the second multiplexer sending the output to the FIFO stage.

4. The mechanism of claim 3, wherein a number of the second multiplexers equals a number of the first registers.

5. The mechanism of claim 1, wherein a value of the delay varies from one clock cycle to N−

1 clock cycles.

6. The mechanism of claim 1, wherein the coalescing prestage comprises one or more multi-ported register arrays, each of the one or more multi-ported register arrays coupled to multiple channels and having a data bandwidth equal to or greater than a data bandwidth of the multiple channels coupled thereto.

7. The mechanism of claim 6, wherein each of the one or more multi-ported register arrays comprises a data depth equal to a data capacity of the multiple channels coupled thereto.

8. The mechanism of claim 6, wherein each channel of the multiple channels has an independent write port in one of the one or more multi-ported register arrays.

9. The mechanism of claim 6, wherein the multiported register arrays each comprise multiple read ports.

10. The mechanism of claim 1, wherein the bundled first-in/first-out stage comprises a combined register stage, comprising one or more primary register arrays, each of the one or more primary register arrays having a plurality of logical register arrays.

11. The mechanism of claim 1, further comprising:

an interface configuration control;

a separate first agent control coupled to the interface configuration control, the first agent control providing first entry locations for writing data to and reading data from the bundled FIFO stage; and

a separate second agent control coupled to the interface configuration control, and operating independently of the first agent control, the second agent control providing second entry locations for writing data to and reading data from the bundled FIFO stage.

12. A method for reconfiguring first-in/first-out registers to support multiple channels in bundled agent configurations, comprising:

receiving data from one or more agents, each of the one or more agents providing the data on one of multiple channels;

coalescing the received data wherein the coalescing, comprises;

receiving the data from the one or more agents in increments of X/N data bits, wherein X represents a capacity of first registers and X/N represents a capacity of a channel, and

storing one X/N increment of data bits in a second register to delay receipt of the one X/N increment of data bits by a first register; and

writing the coalesced data to one of a plurality of bundled first-in/first-out register arrays.

13. The method of claim 12, wherein coalescing the received data further comprises multiplexing outputs from the first registers.

14. The method of claim 12, wherein the coalescing comprises storing the received data in one or more multi-ported register arrays.

15. The method of claim 12, wherein the multi-ported register arrays comprise independent write ports corresponding to each channel of the multiple channels, and further comprising, writing data from a specific channel using a specific independent write port.

16. The method of claim 12, wherein the multi-ported register arrays comprise multiple independent read ports, and further comprising reading data from the multi-ported register arrays using specific read ports.

17. The method of claim 12, wherein writing the coalesced data comprises writing the coalesced data to logical register arrays in each of the plurality of bundled first-in/first-out register arrays.

18. The method of claim 12, wherein the coalescing comprises bundling two or more channels to provide bundled data.

19. An apparatus that provides a reconfigurable first-in/first-out (FIFO) for multiple channels and multiple agents, comprising:

a coalescing prestage, comprising;

a plurality of multiple register sets, the multiple registers in each set servicing one or more agents, wherein the one or more agents provide data for loading into the multiple registers, and

second register sets capable of storing X/N data bits, the second registers coupled to specified ones of the multiple register sets, wherein the second registers store the X/N data bits to impose a daily in unloading the specified register sets; and

a plurality of selection device sets, each selection device set corresponding to one of the multiple register sets, wherein the selection device sets control unloading and loading of selected registers in the multiple register sets; and

a primary FIFO storage coupled to the coalescing prestage, comprising a primary storage device having one or more logical storage areas, wherein data from each agent of the one or more agents is mapped to specified locations in the primary storage device.

20. The apparatus of claim 19, further comprising:

an interface configuration control;

a first agent control coupled to the interface configuration control, the first agent control providing first entry locations for writing data to and reading data from the primary storage device; and

a second agent control coupled to the interface configuration control, the second agent control providing second entry locations for writing data to and reading data from the primary storage device.