High availability computing system

• US 6,594,735 B1
• Filed: 12/28/1998
• Issued: 07/15/2003
• Est. Priority Date: 12/28/1998
• Status: Expired due to Fees

• Current Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Baker, Brian, Newell, Terry E., Wong, Bing L.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): WHITMORE, STACY
• Application Number:
  US09/220,861
• Time in Patent Office: 1,660 Days
• Field of Search: 712/32, 712/114, 709/200, 709/201, 709/213-216, 709/245, 709/248, 711/1, 711/100, 711/147-153, 711/202, 711/203, 711/206, 711/209, 711/210, 707/8, 707/9, 707/200-203
• US Class Current: 711/147
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component
• CPC Class Codes: G06F 8/656 while running

Abstract

A high availability computing system having multiple processing elements capable of simultaneous execution of multiple software programs and seamless software upgrades is disclosed. The system comprises multiple processing elements, each processing element capable of accessing memory at processing element memory addresses; and multiple memory modules each having a plurality of alterable memory units, each memory unit identified by a system memory address within a defined address space. The system further includes a memory element interface in communication with each of the memory elements permitting alteration of the defined address space for the memory element. An address mapper is interconnected between each of the processing elements and at least one of the memory elements. The address mapper is capable of mapping a processing element memory address to a global memory address within a defined address space. Thus, the system may allocate memory addresses used by a single one of the memory elements to an address space used by only a single processing element. The system further has access ports to each of the memory elements, thus allowing the single processing element limited access to other memory modules. Conversely, other processing elements may have limited access to the single memory module. As a result, the single computing system may be divided into two logical computing systems. Software upgrades may be loaded into one system, without interrupting the other system.

Claims

1. In a multi-processor computing system comprising first and second processing elements and first and second memory elements interconnected with said processing elements, said first and second memory elements configurable to occupy first and second memory address spaces within a global address space, respectively, each of said first and second processing elements configurable to use an address space that is a subset of said global address space, a method of operating two logical computing systems, comprising:

a. configuring said first memory element to occupy an address space within said global address space used by said first processing element;

b. configuring said second memory element to occupy an address space within said global address space not used by said first processing element;

c. configuring said second processing element to use said second address space, and thus said second memory element; and

d. preventing write access to said first memory element by said second processing element,

e. loading executable software into said second address space, used by said second processing element;

f. executing said executable software on said second processing element;

thereby creating first and second logical computing systems within said multi-processor computing system.

2. The method of claim 1, further comprising:

g. loading operating parameters for said executable software from said first memory element to said second memory element.

3. The method of claim 2, further comprising:

h. notifying said first processing element that said executable software is executing on said second processing element.

4. The method of claim 2, wherein said loading is performed by said second processing element, under control of said first processing element.

5. The method of claim 1, wherein a. to d. are performed by said first processing element under software control.

6. A multi-processor computing system comprising:

first and second processing elements, each processing element capable of accessing memory at processing element memory addresses;

first and second memory elements having a plurality of alterable memory units, each memory unit identified by a system memory address within a defined address space;

a memory element interface in communication with each of said first and second memory elements permitting alteration of its defined address space;

an address mapper interconnected between each of said processing elements and at least one of said memory elements, each said address mapper capable of mapping a processing element memory address to a system memory address within a defined address space;

each of said first and second memory elements comprising an associated port having a first state permitting alteration of memory units of that memory element through its associated port, and a second state preventing alteration of memory units of that memory element through its associated port;

each of said first and second processing elements connected to each of said first and second memory elements, through an associated one of said ports.

7. The system of claim 6, wherein said first and second memory elements are configurable to span different address spaces and wherein said first and second processing elements are configurable to have limited access to said second and first memory elements, respectively.

8. The system of claim 7, wherein said second processing element is configured to have only read access to said first memory element.

9. The system of claim 6, wherein said memory element interface is configurable so that said first and second memory elements occupy identical address spaces.

10. A multi-processor computing system comprising:

first and second memory elements each comprising alterable memory units;

first and second processing elements interconnected with each of said first and second memory elements to read and write from said memory elements;

each memory element comprising;

means to select an address space within a system address space, used by said each memory element; and

means to limit access to said each memory element by each of said first and second processing elements

means for mapping, interconnected between said first and second processing elements and at least one of said first and second memory elements, said means for mapping capable of mapping a processing element memory address to a system memory address, said means for mapping programmable to select a predefined subset of said system memory address space to be used by a given one of said first and second processing elements as an associated processing element address space so that each memory unit may be identified within said each memory element by an address within said system address space and identified to said given one of said first and second processing elements by an address within said associated processing element address space.

11. A multi-processor computing system comprising:

a plurality of processing elements, each capable of accessing memory only within its associated processing element address space;

memory having a plurality of alterable memory units, each memory unit identified by a system memory address within a defined global memory address space;

an address mapper interconnected between each of said processing elements and said memory units, said address mapper capable of mapping a processing element memory address to a global memory address, said address mapper programmable to select a predefined subset of said memory units within said global memory address space to be used by a given one of said processing elements as an associated processing element address space, each memory unit within said subset identified within said memory by an address within said global memory address space, and identified to said given one of said processing elements by an address within said associated processing element address space.

12. The system of claim 11, wherein said memory comprises a plurality of memory elements each spanning a memory element address space that is a portion of said global address space, said system further comprising a memory element interface in communication with each of said memory elements permitting alteration of its memory element address space within said global address space.

13. The system of claim 12, wherein said memory element interface is configurable so that two memory elements can occupy identical memory element address spaces within said global address space.

14. The system of claim 12, wherein each of said processing elements is configurable to have limited access to selected ones of said plurality of memory elements.

15. The system of claim 12, wherein each of said processing elements is configurable to have read-only access to selected ones of said plurality of memory elements.