Integrated design system and method for reducing and avoiding crosstalk

• US 6,594,805 B1
• Filed: 11/13/2001
• Issued: 07/15/2003
• Est. Priority Date: 11/13/2001
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Huang, Tammy T., Tetelbaum, Alexander, Al-Dabagh, Maad A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Dimyan, Magid Y
• Application Number:
  US09/986,912
• Time in Patent Office: 609 Days
• Field of Search: 716/1-21
• US Class Current: 716/115
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A system, method and program for hierarchically designing integrated circuits(ICs). Potential sources of crosstalk are identified in the hierachical design and prior to and during placement and wiring while maintaining the hierachical structure. Blocks are placed and analyzed to determine if all blocks are well behaved and where necessary selectively re-organized to be well behaved. Blockages are inserted blocks to restrict top level wiring to avoid crosstalk. Orthogonal restrictions are placed on top level wiring as well as on top level wire lengths.

Claims

1. A method of integrated circuit design, said method comprising the steps of:

a) placing each block of an integrated circuit design;

b) verifying whether said each block is well behaved;

c) inserting blockages in said each block;

d) routing top level wires to minimize crosstalk between top level wires and block level wires; and

e) checking top level wiring for crosstalk sources.

2. A method as in claim 1 wherein the step (a) of placing said each block of an integrated circuit design comprises routing block level wiring, adjacent wiring layers being oriented orthogonally to each other.

3. A method as in claim 2 wherein the step (b) of verifying whether each block is well behaved comprises determining whether nets to internal block cells are internal nets, whether each input net to each block is connected to a single buffer, and whether each output buffer from said each block only drives external nets.

4. A method as in claim 2 wherein the step (b) of verifying whether said each block is well behaved comprises the steps of:

i) identifying nets that are both external and internal, any identified net being a violation;

ii) identifying underpowered output buffer, any identified buffer being a violation;

iii) identifying port buffer beyond a maximum distance from a connected port, any identified said port buffer being a violation; and

iv) fixing all violations.

5. A method as in claim 4 wherein the step (b)(i) of identifying nets identifies any nets in said each block with both connected internal cells and external cells, and fixing all violations comprises inserting a buffer in each identified said net between connected internal cells and connected external cells, whereby after fixing said all violations, all nets are either an internal net or an external net.

6. A method as in claim 4 wherein the step (b)(ii) of identifying underpowered output buffers identifies buffers driving external nets and having a load exceeding a preselected maximum loadand fixing all violations comprises increasing drive for each identified underpowered output buffer.

7. A method as in claim 4 wherein the step (b)(iii) of identifying port buffers identifies any port having a connected buffer beyond a maximum distance and fixing violations reduces said distance from identified ports to connected port buffers below said maximum distance.

8. A method as in claim 4 wherein the step (c) of inserting blockages comprises inserting blockages around block level wires in each said block, inserted said blockages spacing top level wiring a selected distance from said block level wires within said each block.

9. A method as in claim 8 wherein the step (c) of inserting blockages in each said block further comprises inserting blockages along block perimeters, wherein inserted said blockages space top level wires a selected distance from adjacent said block level wiring.

10. A method as in claim 9 wherein the step (d) of routing top level wires comprises the steps of:

i) setting top level wiring layer orientation through each placed block; and

ii) routing said top level wiring guided by said blockages, top level wiring passing through said each placed block on wiring layers substantially determined by said top level wiring layer orientation.

11. A method as in claim 10 wherein the step (e) of checking said top level wiring for crosstalk sources comprises the steps of:

i) identifying any top level wire exceeding a critical length, any identified said top level wire being a violation;

ii) identifying any parallel run of one said top level wire adjacent a block level wire wherein said parallel run exceeds crosstalk maximum length, any identified said parallel run being a violation; and

iii) identifying any top level wire having a portion longer than said crosstalk maximum length through any of said blocks, any identified said portion being a violation.

12. A method as in claim 11 further comprising the step of:

f) fixing all violations identified in step (e).

13. A method as in claim 12 wherein any top level wires identified in step (e)(i) are segmented in step (f), all top level wire segments being shorter than said critical length.

14. A method as in claim 12 wherein top level wires in parallel runs identified in step (e) (ii) are segmented in step (f), fixed said parallel runs containing top level line segments being shorter than said crosstalk maximum length.

15. A method as in claim 12 wherein said portions of top level wires identified in step (e) (iii) are segmented in step (f), segmented portions in blocks being shorter than said crosstalk maximum length.

16. A method as in claim 1 wherein step (a) includes identifying Tcone paths from a terminating register, calculating a crosstalk overhead for the terminating register, and adding the calculated crosstalk overhead to an SDF file.

17. A method as in claim 1 wherein step (c) includes inserting a blockage at a block level wire to minimize crosstalk between a through-wired top level wire passing a block level wire.

18. A method as in claim 1 wherein step (d) includes identifying a top level wire passing through a block and segmenting the top level wire to avoid exceeding a critical crosstalk length.

19. A circuit design system for designing hierarchically architected integrated circuits, said circuit design system comprising:

means for placing and wiring an integrated circuit;

means for verifying whether blocks of said integrated circuit are well behaved;

means for selectively blocking areas of said blocks, subsequent wiring being presented between blocked areas; and

means for identifying crosstalk sources in said subsequently routed wiring.

20. A circuit design system as in claim 19 further comprising:

means for orienting block level wiring layers, adjacent block level wiring layers being oriented orthogonally to each other.

21. A design system as in claim 20, wherein placed block level wiring layer orientation orients subsequently wired wiring levels.

22. A circuit design system as in claim 21 wherein said means for selectively blocking comprises:

means for spacing subsequently wired wires a selected distance from block level wiring.

23. A circuit design system as in claim 21 wherein said means for checking blocks comprises:

means for identifying any nets connected to inputs to cells contained in one block and connected to inputs to cells external to said one block;

means for identifying whether an output buffer is driving a load exceeding a maximum load for said output buffer; and

means for identifying whether any port is spaced from a connected buffer by a distance exceeding a maximum distance.

24. A circuit design system as in claim 23 wherein said means for identifying crosstalk sources comprises:

means for identifying any top level wires exceeding a critical length;

means for identifying parallel runs of top level wires with block level wires exceeding a crosstalk maximum length;

means for identifying any top level wires having a portion through a block exceeding said crosstalk maximum length; and

means for segmenting identified top level wires.

25. A computer program product for designing integrated circuits, said computer program product comprising a computer usable medium having computer readable code thereon, said computer readable program code comprising:

computer program code means for placing and wiring an integrated circuit;

computer program code means for making circuit blocks well behaved;

computer program code means for blocking areas of said blocks from subsequent wiring; and

computer program code means for identifying crosstalk sources in top level wiring.

26. A computer program product as in claim 25 wherein the computer program code means for placing and wiring comprises:

computer program code means for orienting adjacent wiring layers orthogonally to each other in said circuit blocks.

27. A computer program product as in claim 26 wherein said computer program code means for selectively blocking comprises:

computer program code means for spacing top level wires a selected distance from block level wiring.

28. A computer program product code as in claim 27 wherein said computer program product code means for making circuit blocks well behaved comprises:

computer program code means for identifying any nets connected to inputs to cells contained in one block and connected to inputs to cells contained in one block and connected to inputs to cells external to said one block;

computer program code means for identifying whether an output buffer is driving a load exceeding a maximum load for said output; and

means for identifying any port is spaced from a connected buffer by a distance exceeding a maximum distance.

29. A computer program product as in claim 28 wherein said computer program code means for identifying crosstalk sources comprises:

computer program code means for identifying any top level wires exceeding a critical length;

computer program code means for identifying parallel runs of top level wires with block level wires exceeding a crosstalk maximum length;

computer program code means for identifying any top level wires having a portion through a block exceeding said crosstalk maximum length; and

computer program code means for segmenting identified top level wires.