Translation consistency checking for modified target instructions by comparing to original copy
First Claim
1. In a computer which translates instructions from a target instruction set to a host instruction set and includes means for detecting a change to memory containing a target instruction to which a write is attempted from which a host instruction has been translated, a method for determining if target instructions from which host instructions have been translated have changed since the translation took place including the steps of:
- testing for an indication that the means for detecting may be slowing operation of the computer with respect to particular target instructions which have been translated, responding to an indication provided by the test by;
storing copies of the particular target instructions, disabling the means for detecting for the particular target instructions, and creating a process to replace the means for detecting including the steps of storing data necessary to execute the process, and executing a process to compare the copies and target instructions presently at an address of the particular target instructions when the host instructions are to be executed, and executing the host instructions if the copies and target instructions compare, and disabling the host instructions if the copies and target instructions do not compare.
6 Assignments
0 Petitions
Accused Products
Abstract
A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.
88 Citations
24 Claims
-
1. In a computer which translates instructions from a target instruction set to a host instruction set and includes means for detecting a change to memory containing a target instruction to which a write is attempted from which a host instruction has been translated, a method for determining if target instructions from which host instructions have been translated have changed since the translation took place including the steps of:
-
testing for an indication that the means for detecting may be slowing operation of the computer with respect to particular target instructions which have been translated, responding to an indication provided by the test by;
storing copies of the particular target instructions, disabling the means for detecting for the particular target instructions, and creating a process to replace the means for detecting including the steps of storing data necessary to execute the process, and executing a process to compare the copies and target instructions presently at an address of the particular target instructions when the host instructions are to be executed, and executing the host instructions if the copies and target instructions compare, and disabling the host instructions if the copies and target instructions do not compare. - View Dependent Claims (2, 3, 4, 5, 6)
in which the step of executing a process to compare the copies and target instructions presently at an address of the particular target instructions when the host instructions are to be executed compares all fields of the instructions except data fields fetched by the host instruction. -
6. A method as claimed in claim 1 in which:
-
the step of executing a process to compare the copies and target instructions presently at an address of the particular target instructions when the host instructions are to be executed is disabled if the copies compare until the means for detecting is again disabled, and the means for a change to memory containing a target instruction to which a write is attempted is enabled.
-
-
-
7. A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of:
-
maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address. - View Dependent Claims (8, 9, 10)
in which the step of comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made compares all fields of the instructions except data fields fetched by the host instruction.
-
-
11. In a computer which translates instructions from a target instruction set into a host instruction set, a method for determining whether host instructions remain valid when a target operating system allows writes to target instruction memory comprising the steps of:
-
providing an indication for generating an exception whenever a write occurs to a memory address storing a target instruction which has been translated into a host instruction, disabling a host instruction translated from a target instruction in response to an exception generated by a write to the memory address, detecting when disabling a host instruction in response to a write to the memory address becomes inefficient and storing a copy of the target instruction which has been translated into the host instruction, responding to an attempt to execute the host instruction by comparing the copy of the target instruction with any target instruction at the memory address, executing the host instruction if the target instruction and the copy compare, and disabling the host instruction if the target instruction and the copy differ. - View Dependent Claims (12, 13, 14, 15)
in which the step of responding to an attempt to execute the host instruction by comparing the copy of the target instruction with any target instruction at the memory address is performed for each target instruction in any sequence of target instructions through any store instruction and is performed for remaining target instructions in the sequence after execution of those host instructions translated from the sequence of target instructions through the store instruction of the sequence of target instructions. -
13. A method as claimed in claim 11 including the additional step of ending translation of target instructions and committing state whenever a store to memory containing target instructions occurs.
-
14. A method as claimed in claim 11:
-
including a further step of translating any target instruction which includes a data field which may change into a host instruction which references the target instruction data field, and in which the step of responding to an attempt to execute the host instruction by comparing the copy of the target instruction with any target instruction at the memory address compares all except fields including references to memory addresses of data fields.
-
-
15. A method as claimed in claim 11
in which the step of responding to an attempt to execute the host instruction by comparing the copy of the target instruction with any target instructions at the memory address is disabled if the copies compare until a next indication for generating an exception, and re-enabling the indication for generating an exception whenever a write occurs to a memory address storing a target instruction which has been translated into a host instruction.
-
-
16. In a computer which translates instructions from a target instruction set into a host instruction set, a method for determining whether host instructions remain valid where a target operating system allows writes to target instruction memory comprising the steps of:
-
translating a sequence of target instructions stored at memory addresses into a sequence of host instructions, storing copies of the target instructions which are being translated into the host instructions, responding to an attempt to execute the sequence of host instructions by comparing the copies of the target instructions with any target instructions at the memory addresses at which the target instructions which were translated were stored when translated into a series of host instructions, executing the sequence of host instructions if the target instructions and the copies compare, and disabling the sequence of host instructions if the target instructions and the copies differ. - View Dependent Claims (17, 18, 19, 20)
in which the step of responding to an attempt to execute the sequence of host instruction by comparing the copies of the target instructions with any target instructions at the memory addresses at which the target instructions which were translated were stored is performed for each target instruction in the sequence of target instructions through any store instruction and is performed for remaining target instructions in the sequence after execution of those of sequence of host instructions translated from the sequence of target instructions through the store instruction of the sequence of target instructions.
-
-
18. A method as claimed in claim 16 in which the step of translating a sequence of target instructions stored at memory addresses into a sequence of host instructions is disabled whenever the sequence of host instructions to be executed includes a store to a memory address at which a target instruction which was translated was stored.
-
19. A method as claimed in claim 16:
-
in which the step of translating a sequence of target instruction stored at memory addresses into a sequence of host instructions comprises the step of translating any target instruction which includes a data field which may vary into a host instruction in which such data field is replaced with a reference to a memory address at which the data field is stored, and in which the step of responding to an attempt to execute the sequence of host instruction by comparing the copies of the target instruction with any target instructions at the memory addresses at which the target instructions which were translated were stored when translated into a series of host instructions compares all except data fields replaced with a reference.
-
-
20. A method as claimed in claim 16:
-
in which the step of responding to an attempt to execute the sequence of host instruction by comparing the copies of the target instruction with any target instructions at the memory addresses at which the target instructions which were translated were stored when translated into a series of host instructions is disabled if the copies compare, and which includes the additional step of providing means for disabling host instructions translated from a target instruction when a write is attempted to such target instruction.
-
-
21. In a computer which translates instructions from a target instruction set into a host instruction set and includes a multiplicity of methods for dealing with writes to target instruction memory, a method including the steps of:
-
disabling a translated instruction, replacing the disabled translated instruction with a Zombie process including a trial translation of a target instruction into a host instruction utilizing a first one of the methods for dealing with the write to the target instruction memory, executing the Zombie process until the trial translation is disabled, and replacing a disabled a trial translation by another of the methods for dealing with the write to the target instruction memory executing target instructions including creating new trial translations. - View Dependent Claims (22, 23, 24)
a new trial translation is enabled and executed whenever a trial translation is disabled.
-
Specification