Manufacturing method for capacitor having electrode formed by electroplating

• US 6,596,149 B2
• Filed: 06/01/1999
• Issued: 07/22/2003
• Est. Priority Date: 06/08/1998
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Horii, Hideki
• Primary Examiner(s): King, Roy
• Assistant Examiner(s): Leader, William T.
• Application Number:
  US09/323,600
• Publication Number:
  US 20010052466A1
• Time in Patent Office: 1,512 Days
• Field of Search: 205/122, 205/264, 205/118, 205/123, 205/170, 205/265, 438/3, 438/255, 438/256, 438/399
• US Class Current: 205/123
• CPC Class Codes: C25D 3/50 of platinum group metals
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

Abstract

A capacitor having an electrode formed by electroplating, and a manufacturing method thereof are disclosed. According to an embodiment of the invention, a conductive film is formed on a conductive plug connected to an active region of a semiconductor substrate, and on an interlayer dielectric (ILD) film formed around the conductive plug. Then, a non-conductive pattern exposing a part of the conductive film on the conductive plug is formed on the conductive film, and a lower electrode, which is formed of a platinum (Pt) group metal, is formed on the conductive film by electroplating. In addition, the lower electrode can have a rectangular, T-shaped, reverse trapezoid or barrel-shaped cross-section. Electroplating can similarly form an upper electrode of the capacitor.

Claims

1. A method of manufacturing a capacitor of a semiconductor memory device, comprising:

(a) forming a conductive film on a conductive plug that connects to an active region of a semiconductor substrate, and on an interlayer dielectric (ILD) film that is around the conductive plug;

(b) forming a non-conductive pattern on the conductive film, the non-conductive pattern exposing a part of the conductive film, the part being on the conductive plug, the non-conductive pattern being formed of one selected from a group consisting of boro-phospho-silicate glass (BPSG), spin-on glass (SOG), phospho-silicate glass (PSG), plasma enhanced SiH₄ (PE-SiH₄) oxide, plasma enhanced tetra-ethyl-ortho-silicate (PE-TEOS) oxide, high density plasma SiO₂ (HDP-SiO₂), high temperature oxide (HTO) film, SiO_x, SiN_x, SiON_x, TiO_x, AlO_x, AlN_x, and mixtures thereof;

(c) immersing the semiconductor substrate, the conductive film, and the non-conductive pattern in an aqueous plating solution; and

(d) forming a metal film of a platinum (Pt) group metal on the exposed part of the conductive film by an electroplating method in which the non-conductive pattern controls an area electroplated to form a lower electrode of the capacitor.

2. The method of claim 1, wherein the conductive film is formed of one selected from a group consisting of Pt group metals, Pt group metal oxides, conductive perovskites, and mixtures thereof.

3. The method of claim 2, wherein the conductive film is formed of one selected from a group consisting of platinum (Pt), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), palladium (Pd), PtO_x, RhO_x, RuO_x, IrO_x, OsO_x, PdO_x, CaRuO₃, SrRuO₃, BaRuO₃, BaSrRuO₃, CaIrO₃, SrIrO₃, BaIrO₃, (La,Sr)CoO₃, and mixtures thereof.

4. The method of claim 1, wherein the lower electrode is formed of one selected from a group consisting of Pt, Ir, Ru, Rh, Os, Pd, and mixtures thereof.

5. The method of claim 1, wherein the plating solution is selected from a group consisting of ammonium platinum nitrite (Pt(NH₃)₂(NO₂)₂), ammonium chloroplatinate ((NH₄)₂PtCl₆) and chloroplatinic acid (H₂PtCl₆).

6. The method of claim 1, wherein the lower electrode is formed to have a rectangular cross-section.

7. The method of claim 1, wherein the lower electrode has a T-shaped cross-section perpendicular to the semiconductor substrate.

8. The method of claim 1, wherein the non-conductive pattern is formed to have a slanted side wall with respect to a direction perpendicular to the conductive film.

9. The method of claim 8, wherein the lower electrode has a trapezoid cross-section that is widest on top and perpendicular to the substrate.

10. The method of claim 1, wherein the lower electrode has a barrel-shaped cross-section perpendicular to the semiconductor substrate.

11. The method of claim 1, further comprising:

(e) removing the non-conductive pattern and the conductive film under the non-conductive pattern to partially expose the ILD film;

(f) forming a dielectric film on the lower electrode and the exposed ILD film; and

(g) forming an upper electrode on the dielectric film.

12. The method of claim 11, wherein the dielectric film is formed of one selected from a group consisting of Ta₂O₅, SrTiO₃ (STO), (Ba,Sr)TiO₃ (BST), PbZrTiO₃ (PZT), SrBi₂Ta₂O₉ (SBT), (Pb,La)(Zr,Ti)O₃, Bi₄Ti₃O₁₂, and mixtures thereof.

13. The method of claim 11, wherein the upper electrode is formed by chemical vapor deposition (CVD) or sputtering.

14. The method of claim 13, wherein the upper electrode is formed of one selected from a group consisting of Pt group metals, Pt group metal oxides, conductive perovskites, and mixtures thereof.

15. The method of claim 14, wherein the upper electrode is formed of one selected from a group consisting of platinum (Pt), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), palladium (Pd), PtO_x, RhO_x, RuO_x, IrO_x, OsO_x, PdO_x, CaRuO₃, SrRuO₃, BaRuO₃, BaSrRuO₃, CaIrO₃, SrIrO₃, BaIrO₃, (La,Sr)CoO₃, and mixtures thereof.

16. The method of claim 11, wherein the step (g) comprises:

(g-1) forming a conductive seed layer on the dielectric film;

(g-2) immersing the semiconductor substrate, the lower electrode, and the dielectric film in an aqueous plating solution; and

(g-3) forming the upper electrode by electroplating a Pt group metal on the seed layer.

17. The method of claim 16, wherein the seed layer is formed by chemical vapor deposition (CVD) or sputtering.

18. The method of claim 16, wherein the seed layer is formed of one selected from a group consisting of Pt group metals, Pt group metal oxides, conductive perovskites, and mixtures thereof.

19. The method of claim 18, wherein the seed layer is formed of one selected from the group consisting of platinum (Pt), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), palladium (Pd), PtO_x, RhO_x, RuO_x, IrO_x, OsO_x, PdO_x, CaRuO₃, SrRuO₃, BaRuO₃, BaSrRuO₃, CaIrO₃, SrIrO₃, BaIrO₃, (La,Sr)CoO₃, and mixtures thereof.

20. The method of claim 16, wherein the upper electrode is formed of one selected from a group consisting of Pt, Ir, Ru, Rh, Os, Pd, and mixtures thereof.

21. The method of claim 16, wherein the upper electrode is formed of Pt and the plating solution used for the electroplating is one selected from a group consisting of ammonium platinum nitrite (Pt(NH₃)₂(NO₂)₂), ammonium chloroplatinate ((NH₄)₂PtCl₆) and chloroplatinic acid (H₂PtCl₆).

22. The method of claim 1, further comprising forming a diffusion barrier film on the conductive plug and the ILD film before the step (a),

wherein the conductive film is formed on the diffusion barrier film in the step (a).

23. The method of claim 22, wherein the diffusion barrier film is formed of one selected from a group consisting of metal nitride, metal silicide, and mixtures thereof.

24. The method of claim 23, wherein the diffusion barrier film is formed of one selected from a group consisting of TiN, TaN, WN, TiSiN, TiAlN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, WSi_x, TiSi_x, CoSi_x, MoSi_x, TaSi_x, and mixtures thereof.

25. The method of claim 22, further comprising:

(e) removing the non-conductive pattern, and the conductive film and the diffusion barrier film under the non-conductive pattern to the extent the ILD film is exposed;

(f) forming a spacer on the exposed ILD film, the spacers covering the exposed side wall of the diffusion barrier film;

(g) forming a dielectric film on the lower electrode and the spacer; and

(h) forming an upper electrode on the dielectric film.

26. The method of claim 25, wherein the spacer is formed of one selected from a group consisting of SOG, HDP-SiO₂, PB-SiH₄, PE-TEOS, SiN_x, SiON_x, BPSG and PSG.

27. The method of claim 25, wherein the step (h) comprises:

(h-1) forming a conductive seed layer on the dielectric film, using a conductive material; and

(h-2) forming the upper electrode by electroplating a Pt group metal on the seed layer.