Thin film transistors

• US 6,596,569 B1
• Filed: 03/15/2002
• Issued: 07/22/2003
• Est. Priority Date: 03/15/2002
• Status: Expired due to Term

• Current Assignee: Alcatel-Lucent USA, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Ho, Peter Kian-Hoon, Loo, Yueh-Lin, Rodgers, John A., Someya, Takao, Bao, Zhenan
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US10/098,201
• Time in Patent Office: 494 Days
• Field of Search: 438/151, 438/149, 438/459, 438/778
• US Class Current: 438/151
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 71/50 Forming devices by joining two substrates together, e.g. lamination techniques
• CPC Class Codes: H10K 77/111 Flexible substrates
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/311 Phthalocyanine
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
• CPC Class Codes: H10K 85/621 Aromatic anhydride or imide compounds, e.g. perylene tetra-carboxylic dianhydride or perylene tetracarboxylic di-imide

Abstract

The specification describes a lamination method for thin film transistor TFT devices wherein each ply of the laminate is a polymer and each contains a portion of the TFT or the interconnection circuit. The plies are laminated together using a solid adhesive polymer layer on the surface of one or both of the plies. The solid adhesive polymer layer has a low elastic modulus that provides effective encapsulation of the TFT, and laminates the plies without high heat or pressure.

Claims

1. A method for manufacturing a thin film transistor (TFT) device, the TFT device comprising TFT elements, comprising the steps of:

a. preparing a first substrate, the substrate comprising a polymer material, by forming a solid adhesive polymer layer on the substrate, and forming at least one TFT element on the solid adhesive polymer layer layer,

b. preparing a second substrate, the substrate comprising a polymer material, by forming at least one TFT element on the substrate, and

c. laminating the first and second substrates together.

2. The method of claim 1 wherein the first and second substrate are continuous tapes.

3. The method of claim 1 wherein the TFT elements on the first substrate comprise source and drain electrodes and the TFT elements on the second substrate comprise TFT gates, gate dielectric layers, and semiconductor layers.

4. The method of claim 1 wherein one of the TFT elements is a gate dielectric layer and the gate dielectric and the solid adhesive polymer layer are the same.

5. The method of claim 1 additionally including the step of forming a solid adhesive polymer layer on the second substrate and forming at least one TFT element on the solid adhesive polymer layer.

6. The method of claim 2 wherein the tapes are reeled onto reels, then reeled off the reels and pressed together to laminate them together.

7. The method of claim 1 wherein the substrates are laminated together at room temperature.

8. The method of claim 1 wherein the substrates are laminated together using UV radiation.

9. The method of claim 1 wherein the solid adhesive polymer layer is PDMS.

10. The method of claim 9 wherein at least one of the substrates comprises PET.

11. The method of claim 1 wherein the substrates are laminated together using a pressure of less than 50 psi.

12. A method for manufacturing a thin film transistor (TFT) device comprising:

a. preparing a first substrate, the substrate comprising a polymer material, by forming a solid adhesive polymer layer on the substrate, and forming the TFT transistor on the solid adhesive polymer layer,

b. preparing a second substrate, the substrate comprising a polymer material, and

c. laminating the first and second substrates together.

13. The method of claim 12 wherein the second substrate has a solid adhesive polymer layer.

14. The method of claim 13 wherein the substrates are laminated together using a pressure of less than 50 psi.

15. A method for manufacturing a thin film transistor (TFT) device comprising:

a. preparing a first substrate, the substrate comprising a polymer material, and forming the TFT device on the polymer material,

b. preparing a second substrate, the substrate comprising a polymer material by forming a solid adhesive polymer layer on the substrate, and

c. laminating the first and second substrates together.

16. The method of claim 15 wherein the substrates are laminated together using a pressure of less than 50 psi.