Method of forming analog capacitor dual damascene process

• US 6,596,579 B1
• Filed: 04/27/2001
• Issued: 07/22/2003
• Est. Priority Date: 04/27/2001
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Randazzo, Todd A., Walker, John de Q., Fuchs, Kenneth P.
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/844,531
• Time in Patent Office: 816 Days
• Field of Search: 438/3, 438/238-240, 438/250-256, 438/381, 438/393-399
• US Class Current: 438/253
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section. Portions of the upper dielectric layer and the second capacitor electrode section are selectively removed to form a first via cavity that extends through the upper dielectric layer and the edge portion of the second capacitor electrode section. This exposes the edge portion of the second capacitor electrode section within the first via cavity. The first via cavity is filled with a via metal, which makes electrical connection with the edge portion of the second capacitor electrode section that is exposed within the first via cavity.

Claims

1. A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein, the process comprising:

(a) forming a capacitor dielectric layer adjacent the upper layer, the capacitor dielectric layer covering the first capacitor electrode section,

(b) forming a second capacitor electrode layer including a second capacitor electrode section adjacent the capacitor dielectric layer, the second capacitor electrode section at least partially covering the first capacitor electrode section and having an edge portion extending beyond the underlying first capacitor electrode section, the capacitor dielectric layer disposed between the first capacitor electrode section and the second capacitor electrode section,

(c) forming an upper dielectric layer adjacent the second capacitor electrode section,

(d) selectively removing portions of the upper dielectric layer to form a first via cavity extending through the upper dielectric layer and at least to the edge portion of the second capacitor electrode section, thereby exposing the edge portion of the second capacitor electrode section within the first via cavity, and

(e) filling the first via cavity with a via metal, the via metal making electrical connection with the edge portion of the second capacitor electrode section exposed within the first via cavity.

2. The process of claim 1 wherein step (d) further includes selectively removing a portion of the second capacitor electrode section and a portion of the capacitor dielectric layer, such that the first via cavity extends through the second capacitor electrode section and at least partially into the capacitor dielectric layer.

3. The process of claim 1 wherein step (a) further comprises forming the capacitor dielectric layer from silicon nitride.

4. The process of claim 1 wherein step (b) further comprises forming the second capacitor electrode layer from titanium nitride.

5. The process of claim 1 wherein step (b) further comprises forming the second capacitor electrode layer from titanium nitride having a thickness of about 250 angstroms.

6. The process of claim 1 wherein:

step (d) further comprises forming a first trench in the upper dielectric layer adjacent the first via cavity using a dual damascene process, and

step (e) further comprises filling the first trench with the via metal to form a first trench metal section having electrical continuity with the second capacitor electrode section.

7. The process of claim 1 wherein the via metal is copper.

8. The process of claim 1 further comprising:

step (b) including forming the second capacitor electrode section such that it does not overly an edge portion of the first capacitor electrode section,

(f) selectively removing a second portion of the upper dielectric layer over the edge portion of the first capacitor electrode section to form a second via cavity extending through the upper dielectric layer and exposing the edge portion of the first capacitor electrode section, and

(g) filling the second via cavity with the via metal, the via metal making electrical connection with the edge portion of the first capacitor electrode section exposed in step (f).

9. The process of claim 8 wherein:

step (f) further comprises forming a second trench in the upper dielectric layer adjacent the second via cavity using a dual damascene process, and

step (g) further comprises filling the second trench with the via metal to form a second trench metal section having electrical continuity with the first capacitor electrode section.

10. The process of claim 1 wherein step (b) further comprises:

(b1) forming a capacitor electrode mask adjacent the second capacitor electrode layer and covering only the second capacitor electrode section, and

(b2) etching the second capacitor electrode layer to remove portions of the second capacitor electrode layer not covered by the capacitor electrode mask.

11. A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein, the process comprising:

(a) forming a capacitor dielectric layer adjacent the upper layer, the capacitor dielectric layer covering the first capacitor electrode section,

(b) forming a second capacitor electrode layer including a second capacitor electrode section adjacent the capacitor dielectric layer, the second capacitor electrode section at least partially covering the first capacitor electrode section and having an edge portion extending beyond the underlying first capacitor electrode section, the capacitor dielectric layer disposed between the first capacitor electrode section and the second capacitor electrode section,

(c) forming an upper dielectric layer adjacent the second capacitor electrode section,

(d) selectively removing portions of the upper dielectric layer, the second capacitor electrode section, and the capacitor dielectric layer to form a first via cavity extending through the upper dielectric layer, the edge portion of the second capacitor electrode section, and the capacitor dielectric layer, thereby exposing the edge portion of the second capacitor electrode section within the first via cavity, and

(e) forming a first trench in the upper dielectric layer adjacent the first via cavity using a dual damascene process, and

(f) filling the first via cavity and the first trench with a via metal, the via metal making electrical connection with the edge portion of the second capacitor electrode section exposed within the first via cavity.

12. The process of claim 11 wherein step (a) further comprises forming the capacitor dielectric layer from silicon nitride.

13. The process of claim 11 wherein step (b) further comprises forming the second capacitor electrode layer from titanium nitride.

14. The process of claim 11 wherein step (b) further comprises forming the second capacitor electrode section of titanium nitride having a thickness of about 250 angstroms.

15. A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section and a via-support metal section therein, the process comprising:

(a) forming a capacitor dielectric layer adjacent the upper layer, the capacitor dielectric layer covering the first capacitor electrode section,

(b) forming a second capacitor electrode layer including a second capacitor electrode section adjacent the capacitor dielectric layer, the second capacitor electrode section covering the via-support metal section and at least partially covering the first capacitor electrode section, the second capacitor electrode section having an edge portion extending beyond the underlying first capacitor electrode section, where the capacitor dielectric layer is disposed between the first capacitor electrode section and the second capacitor electrode section, and between the via-support metal section and the second capacitor electrode section,

(c) forming an upper dielectric layer adjacent the second capacitor electrode section,

(d) selectively removing portions of the upper dielectric layer, the second capacitor electrode section, and the capacitor dielectric layer to form a first via cavity extending through the upper dielectric layer, the edge portion of the second capacitor electrode section, and the capacitor dielectric layer, thereby exposing the edge portion of the second capacitor electrode section within the first via cavity and exposing at least a portion of the underlying via-support metal section, and

(e) filling the first via cavity with a via metal, the via metal making electrical connection with the edge portion of the second capacitor electrode section and the via-support metal section exposed in step (d).

16. A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section formed from copper therein, the process comprising:

(a) forming a capacitor dielectric layer adjacent the upper layer, the capacitor dielectric layer formed from silicon nitride and covering the first capacitor electrode section,

(b) forming a second capacitor electrode layer from titanium nitride having a thickness of about 250 angstroms, the second capacitor electrode layer including a second capacitor electrode section adjacent the capacitor dielectric layer, the second capacitor electrode section at least partially covering the first capacitor electrode section and having an edge portion extending, beyond the underlying first capacitor electrode section, the capacitor dielectric layer disposed between the first capacitor electrode section and the second capacitor electrode section,

(c) forming an upper dielectric layer adjacent the second capacitor electrode section,

(d) selectively removing portions of the upper dielectric layer and the second capacitor electrode section to form a first via cavity extending through the upper dielectric layer and the edge portion of the second capacitor electrode section, thereby exposing the edge portion of the second capacitor electrode section within the first via cavity, and

(e) filling the first via cavity with copper, the copper making electrical connection with the edge portion of the second capacitor electrode section exposed within the first via cavity.