Gate stack for high performance sub-micron CMOS devices

• US 6,596,599 B1
• Filed: 07/16/2001
• Issued: 07/22/2003
• Est. Priority Date: 07/16/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Guo, Jyh-Chyurn
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Foong, Suk San
• Application Number:
  US09/905,403
• Time in Patent Office: 736 Days
• Field of Search: 438/305, 438/287, 438/216, 438/231, 438/302, 438/525, 438/531, 438/944, 438/FOR.188, 438/FOR.240
• US Class Current: 438/305
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Claims

1. A method for creating a gate electrode for high-performance sub-micron CMOS devices, comprising the steps of:

providing a silicon substrate having a bare surface;

depositing a layer of high-k gate dielectric over the surface of said substrate, followed by depositing a layer of bottom gate material over the surface of the layer of gate dielectric, followed by depositing a layer of top gate material over the surface of the layer of bottom gate material;

depositing a layer of hard mask material over the surface of the layer of top gate material followed by depositing a layer of bottom anti reflective coating material over the surface of the layer of hard mask material;

patterning the layer of bottom anti reflective coating material and the layer of hard mask material;

removing the patterned layer of bottom anti reflective coating material;

etching the layer of bottom gate material and the layer of top gate material in accordance with the patterned layer of hard mask material, creating an overhang of the layer of top gate material, exposing a surface area of said layer of high-k gate dielectric;

performing LDD implants into the surface of the substrate;

performing pocket and LDD implants under an angle with the surface of said substrate, said angle being different from a 90 degree angle by an amount;

removing the patterned layer of hard mask material from the surface of the patterned layer of top gate material;

creating first gate spacers over sidewalls of said patterned and etched bottom and top layers of gate material, said first gate spacers comprising a low-k dielectric material;

creating second gate spacers over the surface of said first gate spacers, said second gate spacers comprising TEOS or silicon nitride;

performing source/drain implants into the surface of the substrate, self-aligned with the second gate spacers;

creating salicided contact surface regions to the source and drain regions and the surface of the top layer of gate material; and

removing said first gate spacers from between said patterned and etched layers of top and bottom gate material and said second spacers, said removing comprising;

(i) removing the second gate spacers from above the first gate spacers in upper regions of the first and second gate spacers by polishing the salicided surface of the top layer of gate material, applying methods of Chemical Mechanical Polishing (CMP) to this surface, exposing the first gate spacers;

(ii) creating a photoresist mask overlying the surface of said substrate and the surface of said second gate spacers, said photoresist mask exposing the first gate spacers; and

(iii) applying an isotropic etch to the first gate spacers, thereby removing the first gate spacers.

2. The method of claim 1, the layer of bottom gate electrode material preferably comprising a material selected for the group consisting of polysilicon-germanium and doped polysilicon, the layer of top gate electrode material preferably comprising undoped polysilicon.

3. The method of claim 1, the layer of hard mask material preferably comprising silicon oxynitride.

4. The method of claim 1 with an additional step of annealing the second gate spacers, said additional step being performed prior to performing said source/drain implants.

5. The method of claim 1, said LDD implants into the surface of said substrate being performed perpendicular to the surface of said substrate.

6. The method of claim 1, said pocket implants into the surface of the substrate being performed under an angle with the surface of said substrate, said angle being between about 15 and 45 degrees.

7. The method of claim 1 wherein creating first gate spacers over sidewalls of said patterned and etched layers of bottom and top gate material comprises the steps of:

depositing a first layer of gate spacer material over exposed surface of the layer of gate dielectric, including the surface of the patterned layer of top gate material, said first layer of gate spacer material comprising a low-k dielectric, said first layer of gate spacer material being deposited using methods of spin-coating followed by baking or by methods of CVD; and

etching the deposited first layer of gate spacer material, forming the first gate spacers over the sidewalls of the patterned and etched layers of top and bottom gate material, further removing the exposed layer of gate dielectric from the surface of the substrate, exposing the surface of the substrate.

8. The method of claim 1 wherein creating second gate spacers over the surface of said first gate spacers comprises the steps of:

depositing a second layer of gate spacer material over the exposed surface of the substrate, including the surface of the first gate spacers, said second layer of gate spacer material comprising TEOS or silicon nitride; and

etching said second layer of gate spacer material, forming second gate spacers over the surface of the first gate spacers.

9. A method for creating a gate electrode for high-performance sub-micron CMOS devices, comprising the steps of:

providing a silicon substrate;

performing a gate stack film deposition;

photo patterning and dry etching a hard mask;

performing a gate etch, using the created hard mask as an etch mask, creating a gate structure;

performing an Lightly Doped Diffusion (LDD) impurity implant into the surface of the substrate;

removing the hard mask from the surface of the gate structure;

coating a low-k film over the surface of the gate structure;

creating low-k gate spacers over sidewalls of the gate structure;

creating main gate spacers on the surface of the low-k spacers;

performing source/drain impurity implants into the surface of the substrate, self aligned with the gate structure;

saliciding source/drain surfaces and the surface of the gate structure; and

removing said low-k gate spacers from between said gate structure and said main gate spacers, said removing comprising;

(i) creating openings in the main gate spacers by polishing the surface of the salicided surface of the gate structure, applying methods of Chemical Mechanical Polishing (CMP) to this surface, thereby exposing the low-k gate spacers;

(ii) creating a photoresist mask overlying the surface of said substrate and the surface of said main gate spacers, said photoresist mask exposing the openings created in the main gate spacers, thereby exposing the low-k gate spacers; and

(iii) applying an isotropic etch to the low-k gate spacers, thereby removing the low-k gate spacers.

10. The method of claim 9, said performing a gate stack film deposition comprising the steps of:

depositing a layer of high-k gate dielectric over the surface of said substrate;

then

depositing a layer of bottom gate material over the surface of the layer of high-k gate dielectric; and

then

depositing a layer of top gate material over the surface of the layer of bottom gate material.

11. The method of claim 10, the bottom gate electrode material preferably being selected from the group consisting of polysilicon-germanium or doped polysilicon, the top gate electrode material preferably comprising undoped polysilicon.

12. The method of claim 9 wherein said photo patterning and dry etching a hard mask comprises the steps of:

depositing a layer of hard mask material over the surface of a layer of top gate material;

then

depositing a layer of bottom anti reflective coating over the surface of the layer of hard mask material;

then

patterning and etching the layer of bottom anti reflective coating material and the layer of hard mask material, leaving in place layers of hard mask material and bottom anti reflective coating material that align with the surface region of the substrate over which a gate electrode must be created; and

then

removing the patterned layer of bottom anti reflective coating material, leaving the patterned layer of hard mask material in place over the surface of a layer of top gate material.

13. The method of claim 12, the layer of hard mask material preferably comprising silicon nitride.

14. The method of claim 9 wherein said performing a gate etch, using the created hard mask as an etch mask, creating a gate structure comprises the steps of etching a layer of bottom gate material and a layer of top gate material in accordance with the patterned layer of hard mask material, exposing the surface of a layer of gate dielectric, said etching the layer of bottom gate material and the layer of top gate material comprising applying an overetch to the layer of bottom gate material, creating an overhang of the layer of top gate material.

15. The method of claim 9, said Lightly Doped Diffusion (LDD) impurity implant into the surface of the substrate being performed perpendicular to the surface of said substrate.

16. The method of claim 9, said coating a low-k film over the surface of the gate structure comprising methods of spin-coating followed by baking or by methods of CVD.

17. The method of claim 9, said creating low-k gate spacers over sidewalls of the gate structure comprising the step of etching the low-k film coated over the surface of the gate structure, thereby further removing a layer of gate dielectric from the surface of the substrate, exposing the surface of the substrate.

18. The method of claim 9, said creating main gate spacers of the surface of the low-k spacers comprising the steps of:

depositing a layer of gate spacer material over the exposed surface of the substrate, including the surface of the low-k gate spacers created over sidewalls of the gate structure, said second layer of gate spacer material comprising TEOS or silicon nitride; and

etching said layer of gate spacer material, forming main gate spacers over the surface of the low-k gate spacers.