Programmable memory address decode array with vertical transistors

• US 6,597,037 B1
• Filed: 09/26/2000
• Issued: 07/22/2003
• Est. Priority Date: 02/27/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US09/669,281
• Time in Patent Office: 1,029 Days
• Field of Search: 257/302, 257/319, 257/330, 257/331, 257/314, 257/315
• US Class Current: 257/330
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the decoder. The decoder is programmed at memory test to select an output line responsive to the bits received via the address input lines. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. The control lines are formed together with interconnecting address input lines. The source regions share a common ground while the drain regions are connected to the output lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F² is needed per bit of logic, where F is the minimum lithographic feature size.

Claims

1. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source and drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source and drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source and drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a single control line, substantially adjacent to the floating gate and insulated therefrom, wherein the single control line is associated with a pair of adjacent pillars; and

an intergate dielectric, interposed between the floating gates and the single control line.

2. The floating gate transistor of claim 1, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.

3. The floating gate transistor of claim 1, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

4. The floating gate transistor of claim 1 wherein the floating gate is formed substantially adjacent to two opposing side surfaces of the pillar.

5. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source and drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source and drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source and drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a single control line, substantially adjacent to the floating gate and insulated therefrom, wherein the single control line is associated with a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gates and the single control line; and

a source line located adjacent to the first source and drain region.

6. The floating gate transistor of claim 5 wherein the source line is disposed, at least partially within the substrate.

7. The floating gate transistor of claim 6 wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by ion implantation.

8. The floating gate transistor of claim 6 wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by diffusing dopants into the substrate.

9. The floating gate transistor of claim 5 wherein the source line is located beneath the pillar.

10. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source and drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source and drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source and drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

a plurality of floating gates, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a single control line, wherein the single control line is associated with control gates on a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gate and the control line; and

a source line disposed, at least partially within the substrate, the source line being located adjacent to the first source and drain region.

11. The floating gate transistor of claim 10 wherein the source line is located beneath the pillar.

12. The floating gate transistor of claim 10 wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by ion implantation.

13. The floating gate transistor of claim 10 wherein the source line is comprised of a doped semiconductor of a second conductivity type formed by diffusing dopants into the substrate.

14. A logic cell, comprising:

a transistor located adjacent a substrate having a first and second source and drain region each formed from a single pillar of semiconductor material;

a single control line, wherein the single control line is associated with a pair of adjacent pillars; and

at least one source and drain interconnection line coupled to the transistor at the first source and drain region wherein the source and drain interconnection line is disposed, at least partially within the substrate.

15. The logic cell of claim 14 wherein the source and drain interconnection line is comprised of a doped semiconductor formed by ion implantation.

16. The logic cell of claim 14 wherein the source and drain interconnection line is comprised of a doped semiconductor formed by diffusion of an impurity to induce conductivity.

17. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source and drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source and drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source and drain region;

a pair of floating gates, each substantially adjacent to a portion of the side surface of the pillar and separated therefrom by a gate dielectric;

a single control line, wherein the single control line is associated with a pair of adjacent pillars; and

an intergate dielectric, interposed between the floating gates and the single control line.

18. The floating gate transistor of claim 17, wherein the substrate includes a silicon-on-insulator (SOI) configuration.

19. The floating gate transistor of claim 17, wherein a pitch between control lines on opposite sides of the pillar is approximately twice a minimum lithographic feature size.

20. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source and drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source and drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source and drain region;

a pair of floating gates, each substantially adjacent to a portion of the side surface of the pillar and separated therefrom by a gate dielectric;

a single control line, wherein the single control line is associated with a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gates and the single control line; and

a source line located adjacent to the first source and drain region.

21. The floating gate transistor of claim 20, wherein the substrate includes a silicon-on-insulator (SOI) configuration.

22. The floating gate transistor of claim 20 wherein the source line is disposed, at least partially within the substrate.

23. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source and drain region, of a second conductivity type, formed from a portion of the pillar proximal to the substrate;

a second source and drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source and drain region;

a pair of floating gates, each substantially adjacent to a portion of the side surface of the pillar and separated therefrom by a gate dielectric;

a single control line, wherein the single control line is associated with a pair of adjacent pillars;

an intergate dielectric, interposed between the floating gates and the single control line; and

a source line disposed, at least partially within the substrate, the source line being located adjacent to the first source and drain region.

24. The floating gate transistor of claim 23, wherein the substrate includes a silicon-on-insulator (SOI) configuration.

25. The floating gate transistor of claim 23 wherein the source line is located beneath the pillar.