Narrow high performance MOSFET device design

• US 6,597,043 B1
• Filed: 11/13/2001
• Issued: 07/22/2003
• Est. Priority Date: 11/13/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Naem, Abdalla
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Fenty, Jesse A
• Application Number:
  US10/054,282
• Time in Patent Office: 616 Days
• Field of Search: 257/401, 257/412, 257/413, 257/346, 257/365, 257/366
• US Class Current: 257/387
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out

Abstract

The present invention provides a narrow/short high performance MOS device structure that includes a rectangular-shaped semiconductor substrate region having a first conductivity type. A region of dielectric material is formed at the center of the substrate region. Four substrate diffusion regions, each having a second conductivity type opposite the first conductivity type, are formed in the substrate diffusion region in a respective comer of the substrate region. The four diffusion regions are spaced-apart such that a substrate channel region is defined between each adjacent pair of substrate diffusion regions. A common conductive gate electrode is formed to have four fingers, each one of the fingers extending over a corresponding substrate channel region. The fingers of the common conductive gate electrode are spaced-apart from the underlying substrate channel regions by dielectric material formed therebetween.

Claims

1. A high performance MOSFET transistor structure comprising:

a rectangular-shaped semiconductor substrate region having a first conductivity type;

a region of dielectric material formed in the semiconductor substrate region at a center region of the semiconductor substrate region;

first, second, third and fourth substrate diffusion regions having a second conductivity type opposite the first conductivity type, each substrate diffusion region being formed at a respective comer of the semiconductor substrate region and spaced-apart such that a substrate channel region is defined between each adjacent pair of substrate diffusion regions; and

a common conductive gate electrode having first, second, third and fourth fingers, each finger extending over a corresponding substrate channel region and spaced-apart therefrom by gate dielectric material.

2. A MOSFET transistor structure as in claim 1, and wherein the semiconductor substrate region comprises silicon.

3. A MOSFET transistor structure as in claim 2, and wherein the dielectric material comprises silicon dioxide.

4. A high performance MOSFET transistor structure formed in a silicon substrate having a first conductivity type, the structure comprising:

shallow trench isolation silicon oxide formed in the silicon substrate to define an isolated rectangular silicon device region;

a region of silicon oxide formed in the silicon device region at a center region of the silicon device region;

first, second, third and fourth diffusion regions having a second conductivity type opposite the first conductivity type, each diffusion region being formed in the silicon device region at a respective corner of the silicon device region and spaced-apart such that a channel region is defined in the silicon device region between each adjacent pair of diffusion regions; and

a common conductive gate electrode having first, second, third and fourth fingers, each extending over a corresponding channel region and spaced-apart therefrom by intervening gate dielectric material.

5. A MOSFET transistor structure as in claim 4, and wherein the common conductive gate electrode comprises polysilicon.

6. A MOSFET transistor structure as in claim 4, and wherein the gate dielectric material comprises silicon oxide.