Current mode bidirectional port with data channel used for synchronization

• US 6,597,198 B2
• Filed: 10/05/2001
• Issued: 07/22/2003
• Est. Priority Date: 10/05/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mooney, Stephen R., Martin, Aaron K., Haycock, Matthew B.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tran, Anh
• Application Number:
  US09/972,327
• Publication Number:
  US 20030067325A1
• Time in Patent Office: 655 Days
• Field of Search: 326/30, 326/82, 326/83, 326/86, 326/90, 326/93
• US Class Current: 326/82
• CPC Class Codes: H03K 19/018592 with a bidirectional operation
• CPC Class Codes: H04L 25/45 using electronic distributors
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence

Abstract

A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a data transceiver circuit. The combination data and synchronization transceiver circuit synchronizes the port with another simultaneous bidirectional port coupled to the same bus. The combination data and synchronization transceiver circuit includes a driver with a variable output current and a variable output resistance. Prior to synchronization, the driver has a low output current and low output resistance. When the simultaneous bidirectional port is ready to communicate, the variable output resistance is increased. When both simultaneous bidirectional ports are ready, the variable output resistance is set to properly terminate the line, and the variable output current is set to provide a desired voltage swing.

Claims

1. A bidirectional port circuit comprising:

a current mode output driver having a variable current source;

a synchronization control circuit coupled to the current mode output driver to control the variable current source during an initialization sequence; and

an initialization circuit coupled to the current mode output driver to control the variable current source other than during the initialization sequence.

2. The bidirectional port circuit of claim 1 further comprising:

a variable termination resistor coupled to an output node of the current mode output driver to present a termination resistance value.

3. The bidirectional port circuit of claim 2 wherein:

the synchronization control circuit is coupled to the variable termination resistor to control the termination resistance value during the initialization sequence; and

the initialization circuit is coupled to the variable termination resistor to control the termination resistance value other than during the initialization sequence.

4. The bidirectional port circuit of claim 2 wherein the synchronization control circuit is operable to control both the variable current source and the variable termination resistor during the initialization sequence.

5. The bidirectional port circuit of claim 4 further including a synchronization receiver coupled to the output node to detect changes made by the synchronization control circuit.

6. The bidirectional port circuit of claim 2 wherein the initialization circuit is operable to control both the variable current source and the variable termination resistor other than during the initialization sequence.

7. The bidirectional port circuit of claim 2 wherein the synchronization control circuit is operable to increase the termination resistance value in response to the initialization circuit.

8. The bidirectional port circuit of claim 1 further including a data transceiver responsive to the initialization circuit.

9. The bidirectional port circuit of claim 1 wherein:

the current mode output driver is part of a first data transceiver;

the bidirectional port circuit comprises a plurality of data transceivers of which the first data transceiver is one, the plurality of data transceivers being arranged from a most significant bit to a least significant bit; and

the first data transceiver is the most significant bit.

10. The bidirectional port circuit of claim 1 wherein:

the current mode output driver is part of a first data transceiver;

the bidirectional port circuit comprises a plurality of data transceivers of which the first data transceiver is one, the plurality of data transceivers being arranged from a most significant bit to a least significant bit; and

the first data transceiver is the least significant bit.

11. An integrated circuit having a bidirectional port comprising:

a first data transceiver capable of being initialized;

an initialization circuit to initialize the first data transceiver; and

a second data transceiver operable to present a reduced output current when the first data transceiver is being initialized, and to present an increased output current thereafter.

12. The integrated circuit of claim 11 wherein the second data transceiver comprises:

an output node;

a variable current source coupled to the output node; and

a variable termination resistor coupled to the output node.

13. The integrated circuit of claim 12 further comprising a synchronization control circuit coupled to the variable current source and the variable termination resistor.

14. The integrated circuit of claim 13 further comprising:

a multiplexor coupled to an input node of the second data transceiver, the multiplexor configured to drive the second data transceiver with a signal from the synchronization control circuit or a data signal from within the integrated circuit.

15. The integrated circuit of claim 11 wherein:

the first data transceiver includes a variable termination resistor; and

the initialization circuit is operable to initialize the variable termination resistor of the first data transceiver.

16. The integrated circuit of claim 11 wherein the bidirectional port includes a plurality of data transceivers other than the first and second data transceivers.

17. The integrated circuit of claim 16 wherein the first, second, and plurality of data transceivers form a bus arranged from most significant bit to least significant bit, and the second data transceiver is the most significant bit.

18. The integrated circuit of claim 16 wherein the first, second, and plurality of data transceivers form a bus arranged from most significant bit to least significant bit, and the second data transceiver is the least significant bit.

19. An integrated circuit comprising:

a synchronization control circuit;

an initializable data driver having an output node to drive a first data node external to the integrated circuit;

a combination data and synchronization driver responsive to the synchronization control circuit to present a variable output current and termination resistance to a second data node external to the integrated circuit as a function of whether the data driver has been initialized; and

a synchronization receiver having an input node coupled to the second data node external to the integrated circuit, and having an output node coupled to the synchronization control circuit.

20. The integrated circuit of claim 19 wherein the data driver includes a variable termination resistance coupled to the first data node external to the integrated circuit.

21. The integrated circuit of claim 20 further comprising an initialization circuit to initialize the variable termination resistance of the data driver.

22. The integrated circuit of claim 19 wherein the integrated circuit is a circuit type from the group comprising:

a processor, a processor peripheral, a memory, and a memory controller.

23. The integrated circuit of claim 19 wherein:

the data driver is part of a first data transceiver, the first data transceiver further comprising a receiver having an input node coupled to the first data node external to the integrated circuit; and

the combination output and synchronization driver is part of a second data transceiver, the second data transceiver further comprising a second receiver having an input node coupled to the second data node external to the integrated circuit.

24. An electronic system comprising:

a first integrated circuit including a first simultaneous bidirectional port comprising a first data driver, a first data receiver, and a first combination data and synchronization driver having a variable output current and a variable output resistance, the first integrated circuit further including a first synchronization control circuit operable to set the variable output current and the variable output resistance of the first combination data and synchronization driver; and

a second integrated circuit including a second simultaneous bidirectional port comprising a second data driver, a second data receiver, and a second combination data and synchronization driver having a variable output current and a variable output resistance, the second integrated circuit further including a second synchronization control circuit operable to set the variable output current and the variable output resistance of the second combination data and synchronization driver;

wherein output nodes of the first and second data drivers are coupled in common with input nodes of the first and second data receivers, and output nodes of the first and second combination data and synchronization drivers are coupled in common.

25. The electronic system of claim 24 wherein the first synchronization control circuit is operable to set the variable output current and the variable output resistance of the first combination data and synchronization driver during an initialization state.

26. The electronic system of claim 25 wherein the first integrated circuit further comprises a first initialization circuit, and wherein the first initialization circuit is operable to set a variable output current and a variable output resistance of the first data driver during the initialization state.

27. The electronic system of claim 26 wherein the first initialization circuit is operable to set the variable output current and the variable output resistance of the first combination data and synchronization driver after the initialization state.