CMOS gate array with vertical transistors

• US 6,597,203 B2
• Filed: 03/14/2001
• Issued: 07/22/2003
• Est. Priority Date: 03/14/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US09/808,369
• Publication Number:
  US 20020130686A1
• Time in Patent Office: 860 Days
• Field of Search: 326/93, 326/95, 326/96, 326/97, 326/98, 326/101, 326/112, 326/119, 326/83
• US Class Current: 326/98
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

Structures and methods for CMOS gate arrays with vertical transistors are provided. The CMOS gate arrays with vertical transistors comprise a logic circuit. The logic circuit includes a dynamic pull-down circuit having a number of logic inputs, a clock input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output. The logic circuit further includes a static pull-up circuit having a number of logic inputs, a clock bar input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output. And, the dynamic pull down circuit is cascaded with the static pull up circuit such that one of the number of inputs for the pull up circuit is coupled to the output of the pull down circuit.

Claims

1. A logic circuit, comprising:

a dynamic pull-down circuit, the pull-down circuit including a number of logic inputs coupled to a number of gates for free standing vertical n-channel transistors, and a clock input coupled to a gate of a free standing vertical p-channel transistor for precharging an output of the pull down circuit;

a static pull-up circuit, the pull-up circuit including a number of logic inputs coupled to a number of gates for free standing vertical n-channel transistors, and a clock bar input coupled to a gate of a free standing vertical n-channel transistor for precharging an output of the pull up circuit, wherein one of the number of inputs for the pull up circuit is coupled to the output of the pull down circuit.

2. The logic circuit of claim 1, wherein the clock input coupled to the gate of the free standing vertical p-channel transistor is configured for precharging the output of the pull down circuit high prior to the arrival of a number of logic input signals at the number of logic inputs.

3. The logic circuit of claim 1, wherein the clock bar input coupled to the gate of the free standing vertical n-channel transistor is configured for precharging the output of the pull up circuit low prior to the arrival of a number of logic input signals at the number of logic inputs.

4. The logic circuit of claim 1, wherein the free standing vertical p-channel transistor of the pull down circuit, having a gate coupled to the clock input, has a channel coupled between a power supply and the output.

5. The logic circuit of claim 1, wherein the free standing vertical n-channel transistor of the pull up circuit, having a gate coupled to the clock bar input, has a channel coupled between a low voltage supply and the output.

6. A logic circuit, comprising:

a dynamic logic circuit having a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output;

a static logic circuit, having a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output, and wherein one of the number of inputs for the static logic circuit is coupled to the output of the dynamic logic circuit.

7. The logic circuit of claim 6, wherein the output of the static logic circuit is coupled to a logic input for a subsequent dynamic logic circuit.

8. The logic circuit of claim 6, wherein the free standing vertical p-channel transistor in the dynamic logic circuit is coupled between a power supply and the output for precharging the output of the dynamic logic circuit high.

9. The logic circuit of claim 8, wherein the free standing vertical p-channel transistor in the dynamic logic circuit is configured for precharging the output prior to an arrival of a number of input signals on the number of logic inputs of the dynamic logic circuit.

10. The logic circuit of claim 6, wherein the free standing vertical n-channel transistor in the static logic circuit, having a gate coupled to the clock bar input, is coupled between a low voltage supply and the output for precharging the output of the static logic circuit low.

11. The logic circuit of claim 10, wherein the free standing vertical n-channel transistor in the static logic circuit, having a gate coupled to the clock bar input, is configured for precharging the output prior to an arrival of a number of input signals on the number of logic inputs of the static logic circuit.

12. A monotonic dynamic-static pseudo-NMOS logic circuit, comprising:

a dynamic logic circuit having a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output high;

a static logic circuit, having a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output low, and wherein one of the number of inputs for the static logic circuit is coupled to the output of the dynamic logic circuit.

13. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 12, wherein the output of the static logic circuit is coupled to a logic input for a subsequent dynamic logic circuit.

14. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 12, wherein the free standing vertical p-channel transistor in the dynamic logic circuit is coupled between a power supply and the output for precharging the output of the dynamic logic circuit during a precharge stage.

15. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 14, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors are configured for receiving a number of input signals during an evaluation stage when the clock input receives a high signal.

16. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 12, wherein the free standing vertical n-channel transistor in the static logic circuit, having a gate coupled to the clock bar input, is coupled between a low voltage supply and the output for precharging the output of the static logic circuit during a precharge stage.

17. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 16, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock bar input receives a low signal.

18. A monotonic dynamic-static pseudo-NMOS logic circuit, comprising:

a dynamic logic circuit having a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor coupled between a power supply and the output for precharging the output of the dynamic logic circuit during a precharge stage;

a static logic circuit, having a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor coupled between a low voltage supply and the output for precharging the output of the static logic circuit during a precharge stage; and

wherein one of the number of inputs for the static logic circuit is coupled to the output of the dynamic logic circuit.

19. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 18, wherein the output of the static logic circuit is coupled to a logic input for a subsequent dynamic logic circuit.

20. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 18, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the dynamic logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock input receives a high signal.

21. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 18, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock bar input receives a low signal.

22. A monotonic dynamic-static pseudo-NMOS logic circuit, comprising:

a dynamic logic circuit having a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor wherein the free standing vertical p-channel transistor in the dynamic logic circuit is coupled between a power supply and the output for precharging the output of the dynamic logic circuit high during a precharge stage prior to an arrival of a number of input signals on the number of logic inputs of the dynamic logic circuit;

a static logic circuit, having a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor which is coupled between a low voltage supply and the output for precharging the output of the static logic circuit low during a precharge stage prior to an arrival of a number of input signals on the number of logic inputs of the static logic circuit, and wherein one of the number of inputs for the static logic circuit is coupled to the output of the dynamic logic circuit.

23. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 22, wherein the output of the static logic circuit is coupled to a logic input for a subsequent dynamic logic circuit.

24. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 22, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the dynamic logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock input receives a high signal.

25. The monotonic dynamic-static pseudo-NMOS logic circuit of claim 22, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock bar input receives a low signal.

26. A CMOS gate array, comprising:

a dynamic logic circuit having a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output;

a static logic circuit, having a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output, and wherein one of the number of inputs for the static logic circuit is coupled to the output of the dynamic logic circuit; and

wherein each of the free standing vertical transistors includes;

a vertically stacked body region and first and second source/drain regions formed within a pillar of semiconductor material extending outwardly from a working surface of a substrate, the pillar having an upper surface and a number of sides; and

a gate associated with a side of the pillar and located below the upper surface of the pillar.

27. The CMOS gate array of claim 26, wherein the gates for the free standing vertical transistors include vertically oriented gates.

28. The CMOS gate array of claim 26, wherein the gates for the free standing vertical transistors include horizontally oriented gates.

29. A CMOS gate array, comprising:

a number of dynamic logic circuits, each dynamic logic circuit including a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output;

a number of static logic circuits, each static logic circuit including a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output; and

wherein number of dynamic logic circuits and the number of static logic circuits are cascaded such that the output of one dynamic logic circuit is coupled to one of the number of logic inputs for a subsequent static logic circuit, and the output of one of the static logic circuits is coupled to the one of the number of logic inputs for a subsequent dynamic logic circuit.

30. The CMOS gate array of claim 29, wherein the free standing vertical p-channel transistor in each dynamic logic circuit is coupled between a power supply and the output for precharging the output of the dynamic logic circuit high.

31. The CMOS gate array of claim 30, wherein the free standing vertical p-channel transistor in the dynamic logic circuit is configured for precharging the output prior to an arrival of a number of input signals on the number of logic inputs of the dynamic logic circuit.

32. The CMOS gate array of claim 29, wherein the free standing vertical n-channel transistor in each static logic circuit, having a gate coupled to the clock bar input, is coupled between a low voltage supply and the output for precharging the output of the static logic circuit low.

33. The CMOS gate array of claim 32, wherein the free standing vertical n-channel transistor in the static logic circuit, having a gate coupled to the clock bar input, is configured for precharging the output prior to an arrival of a number of input signals on the number of logic inputs of the static logic circuit.

34. A CMOS gate array, comprising:

a number of dynamic logic circuits, each dynamic logic circuit including a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output high;

a number of static logic circuits, each static logic circuit including a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output low; and

wherein number of dynamic logic circuits and the number of static logic circuits are cascaded such that the output of one dynamic logic circuit is coupled to one of the number of logic inputs for a subsequent static logic circuit, and the output of one of the static logic circuits is coupled to the one of the number of logic inputs for a subsequent dynamic logic circuit.

35. The CMOS gate array of claim 34, wherein the free standing vertical p-channel transistor in each dynamic logic circuit is coupled between a power supply and the output for precharging the output of the dynamic logic circuit during a precharge stage.

36. The CMOS gate array of claim 35, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors are configured for receiving a number of input signals during an evaluation stage when the clock input receives a high signal.

37. The CMOS gate array of claim 34, wherein the free standing vertical n-channel transistor in each static logic circuit, having a gate coupled to the clock bar input, is coupled between a low voltage supply and the output for precharging the output of the static logic circuit during a precharge stage.

38. The CMOS gate array of claim 37, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock bar input receives a low signal.

39. A CMOS gate array, comprising:

a number of dynamic logic circuits, each dynamic logic circuit including a number of logic inputs, a clock input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, and the clock input is coupled to a gate of a free standing vertical p-channel transistor coupled between a power supply and the output for precharging the output high during a precharge stage prior to an arrival of a number of input signals on the number of logic inputs of the dynamic logic circuit;

a number of static logic circuits, each static logic circuit including a number of logic inputs, a clock bar input, and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, the clock bar input is coupled to a gate of a free standing vertical n-channel transistor coupled between a low voltage supply and the output of the static logic circuit for precharging the output low during a precharge stage prior to an arrival of a number of input signals on the number of logic inputs of the static logic circuit;

wherein number of dynamic logic circuits and the number of static logic circuits are cascaded such that the output of one dynamic logic circuit is coupled to one of the number of logic inputs for a subsequent static logic circuit, and the output of one of the static logic circuits is coupled to the one of the number of logic inputs for a subsequent dynamic logic circuit; and

wherein each of the free standing vertical transistors includes;

a vertically stacked body region and first and second source/drain regions formed within a pillar of semiconductor material extending outwardly from a working surface of a substrate, the pillar having an upper surface and a number of sides; and

a gate associated with a side of the pillar and located below the upper surface of the pillar.

40. The CMOS gate array of claim 39, wherein the gates for the free standing vertical transistors include vertically oriented gates.

41. The CMOS gate array of claim 39, wherein the gates for the free standing vertical transistors include horizontally oriented gates.

42. The CMOS gate array of claim 39, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the dynamic logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock input receives a high signal.

43. The CMOS gate array of claim 39, wherein the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit are configured for receiving a number of input signals during an evaluation stage when the clock bar input receives a low signal.

44. The CMOS gate array of claim 39, wherein cascading a number of dynamic logic circuits and a number of static logic circuits, each circuit having a number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors includes providing a number of logic inputs in the static logic circuit which are configured to receive a number of input signals during an evaluation stage when the clock bar input receives a low signal.

45. A method for performing logic functions, comprising:

coupling a dynamic logic circuit to a static logic circuit, each having a number of logic inputs and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, wherein the dynamic logic circuit further includes a clock input and the static logic circuit includes a clock bar input, and wherein one of the number of inputs for the static logic circuit is coupled to the output of the dynamic logic circuit;

precharging the output of the dynamic logic circuit during a precharge stage by providing a low clock signal to the clock input, the clock input being coupled to a gate of a free standing vertical p-channel transistor coupled between a power supply and the output; and

precharging the output of the static logic circuit during the precharge stage by providing a high clock signal to the clock bar input, the clock bar input being coupled to a gate of a free standing vertical n-channel transistor coupled between a low voltage supply and the output.

46. The method of claim 45, wherein the method further includes providing an output signal from the output of the static logic circuit to one of a number of logic inputs for a subsequent dynamic logic circuit.

47. The method of claim 45, wherein the method further includes receiving a number of input signals at the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the dynamic logic circuit during an evaluation stage, wherein the clock input receives a high signal during the evaluation stage.

48. The method of claim 45, wherein the method further includes receiving a number of input signals at the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit during the evaluation stage, wherein the clock bar input receives a low signal during the evaluation stage.

49. A method for operating a CMOS gate array, comprising:

coupling a static logic circuit to a dynamic logic circuit, each having a number of logic inputs and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, wherein the static logic circuit further includes a clock bar input and the dynamic logic circuit includes a clock input, and wherein one of the number of inputs for the dynamic logic circuit is coupled to the output of the static logic circuit;

precharging the output of the static logic circuit during a precharge stage prior to an arrival of a number of input signals on the number of logic inputs of the static logic circuit by providing a high clock signal to the clock bar input, the clock bar input being coupled to a gate of a free standing vertical n-channel transistor coupled between a low voltage supply and the output; and

precharging the output of the dynamic logic circuit during the precharge stage prior to an arrival of a number of input signals on the number of logic inputs of the dynamic logic circuit by providing a low clock signal to the clock input, the clock input being coupled to a gate of a free standing vertical p-channel transistor coupled between a power supply and the output.

50. The method of claim 49, wherein the method further includes providing an output signal from the output of the dynamic logic circuit to one of a number of logic inputs for a subsequent static logic circuit.

51. The method of claim 49, wherein the method further includes receiving a number of input signals at the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit during an evaluation stage, wherein the clock bar input receives a low signal during the evaluation stage.

52. The method of claim 49, wherein the method further includes receiving a number of input signals at the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the dynamic logic circuit during the evaluation stage, wherein the clock input receives a high signal during the evaluation stage.

53. A method for forming a logic circuit, comprising:

coupling a dynamic logic circuit to a static logic circuit, each having a number of logic inputs and an output, wherein the number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors, wherein the dynamic logic circuit further includes a clock input and the static logic circuit includes a clock bar input, and wherein one of the number of inputs for the static logic circuit is coupled to the output of the dynamic logic circuit;

coupling the clock input to a gate of a free standing vertical p-channel transistor coupled between a power supply and the output of the dynamic logic circuit for precharging the output during a precharge stage; and

coupling the clock bar input to a gate of a free standing vertical n-channel transistor coupled between a low voltage supply and the output of the static logic circuit for precharging the output during a precharge stage.

54. The method of claim 53, wherein the method further includes coupling the output of the static logic circuit to a logic input for a subsequent dynamic logic circuit.

55. The method of claim 53, wherein the method further includes configuring the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the dynamic logic circuit to receive a number of input signals during an evaluation stage when the clock input receives a high signal.

56. The method of claim 53, wherein the method further includes configuring the number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors in the static logic circuit to receive a number of input signals during an evaluation stage when the clock bar input receives a low signal.

57. A method of forming a CMOS gate array, comprising:

cascading a number of dynamic logic circuits and a number of static logic circuits, each circuit having a number of logic inputs and an output, wherein the number of logic inputs in each circuit are coupled to a number of gates of free standing vertical n-channel transistors, wherein each dynamic logic circuit further includes a clock input and each static logic circuit includes a clock bar input;

coupling the clock input in each dynamic logic circuit to a gate of a free standing vertical p-channel transistor coupled between a power supply and the output of the dynamic logic circuit for precharging the output during a precharge stage prior to the arrival of a number of input signals to the number of logic inputs;

coupling the clock bar input in each static logic circuit to a gate of a free standing vertical n-channel transistor coupled between a low voltage supply and the output of the static logic circuit for precharging the output during the precharge stage prior to the arrival of a number of input signals to the number of logic inputs;

wherein cascading the number of dynamic logic circuits and the number of static logic circuits includes cascading the circuits such that the output of one dynamic logic circuit is coupled to one of the number of logic inputs for a subsequent static logic circuit, and the output of one of the static logic circuits is coupled to the one of the number of logic inputs for a subsequent dynamic logic circuit; and

wherein forming each of the free standing vertical transistors includes;

forming a vertically stacked body region and first and second source/drain regions formed within a pillar of semiconductor material extending outwardly from a working surface of a substrate, the pillar having an upper surface and a number of sides; and

forming a gate associated with a side of the pillar and located below the upper surface of the pillar.

58. The method of claim 57, wherein forming the gates for the free standing vertical transistors includes forming vertically oriented gates.

59. The method of claim 57, wherein forming the gates for the free standing vertical transistors includes forming horizontally oriented gates.

60. The method of claim 57, wherein forming each of the free standing vertical transistors includes forming the free standing vertical transistors on a silicon on insulator substrate.

61. The method of claim 57, wherein forming each of the free standing vertical transistors includes undercutting the pillars and oxidizing the substrate to isolate the pillars from the substrate.

62. The method of claim 57, wherein cascading a number of dynamic logic circuits and a number of static logic circuits, each circuit having a number of logic inputs coupled to the number of gates of free standing vertical n-channel transistors includes providing a number of logic inputs in the dynamic logic circuit which are configured to receive a number of input signals during an evaluation stage when the clock input receives a high signal.