Circuits and methods for slew rate control and current limiting in switch-mode systems
First Claim
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1. A switched-mode amplifier current control apparatus comprising:
- a driver amplifier configurable for selective operation in a first, second and third operating mode; and
a bias circuitry configured for selective coupling to said driver amplifier, said bias circuitry operable for limiting an output current of said driver amplifier in said first operating mode, and wherein said driver amplifier is operable for transitioning from said first operating mode to a selected one of said second and third operating modes in response to a state of an output node of said driver amplifier.
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Abstract
An apparatus and method for limiting the output current in a switched mode amplifier are implemented. The apparatus includes a driver amplifier configurable for selective operation in one of three modes. The amplifier is operable for transitioning between the first mode and one of the second and third modes in response to a state of an output node of the driver. Bias circuitry, configurable for selective coupling to the driver amplifier is operable for limiting the output current of the amplifier in the first operating mode.
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Citations
33 Claims
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1. A switched-mode amplifier current control apparatus comprising:
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a driver amplifier configurable for selective operation in a first, second and third operating mode; and
a bias circuitry configured for selective coupling to said driver amplifier, said bias circuitry operable for limiting an output current of said driver amplifier in said first operating mode, and wherein said driver amplifier is operable for transitioning from said first operating mode to a selected one of said second and third operating modes in response to a state of an output node of said driver amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
a reference signal;
a comparator having a first input coupled to said reference signal and a second input coupled to an output node of said driver amplifier;
a control circuitry coupled to an output of said comparator, said control circuitry selecting said second state in response to a value of said output of said comparator and a predetermined timing condition.
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6. The apparatus of claim 5 wherein said reference signal comprises a predetermined reference voltage.
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7. The apparatus of claim 5 further comprising reference circuitry, and wherein said reference signal comprises a signal at a reference node of said reference circuitry.
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8. The apparatus of claim 7 wherein said reference node comprises a junction of a current source, a drain of a field effect transistor (FET), and a capacitor.
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9. The apparatus of claim 5 wherein said predetermined timing condition comprises an expiry of a predetermined delay.
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10. The apparatus of claim 5 wherein said predetermined timing condition comprises a relative transition rate between a reference node and said output node of said driver amplifier.
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11. The apparatus of claim 2 wherein, in said first state, said bias circuit and said driver amplifier form a current mirror.
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12. A current control method comprising the steps of:
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switching a bias circuit operable for limiting an output current of an amplifier to an input of said amplifier; and
determining if a voltage at an output node of said amplifier satisfies a predetermined condition. - View Dependent Claims (13, 14, 15, 16, 17, 18)
if said value of said input signal is a first value, said voltage at said output node is less than a first reference signal; and
if said value of said input signal is a second value, said voltage at said output node is greater than a second reference signal.
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17. The method of claim 12 wherein said predetermined condition comprises, a transition rate of said output node exceeds a transition rate of a reference node.
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18. The method of claim 17 wherein said reference node comprises a node of a current source, a drain of a field effect transistor (FET) and a capacitor.
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19. An amplifier system comprising:
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a digital signal source;
a driver amplifier configurable for selective operation in a first, second and third operating mode; and
a bias circuitry configured for selective coupling to said driver amplifier, said bias circuitry operable for limiting an output current of said driver amplifier in said first operating mode, and wherein said driver amplifier is operable for transitioning from said first operating mode to a selected one of said second and third operating modes in response to a state of an output node of said driver amplifier; and
a pulse width modulator coupled to said digital signal source, an output of said pulse width modulator controlling a duty cycle of said driver amplifier. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
a reference signal;
a comparator having a first input coupled to said reference signal and a second input coupled to an output node of said driver amplifier;
control circuitry coupled to an output of said comparator, said control circuitry selecting said second state in response to a value of said output of said comparator and a predetermined timing condition.
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25. The system of claim 24 wherein said reference signal comprises a predetermined reference voltage.
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26. The system of claim 24 further comprising reference circuitry, and wherein said reference signal comprises a signal at a reference node of said reference circuitry.
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27. The system of claim 26 wherein said reference node comprises a junction of a current source, a drain of a field effect transistor (FET), and a capacitor.
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28. The system of claim 24 wherein said predetermined timing condition comprises an expiry of a predetermined delay.
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29. The system of claim 24 wherein said predetermined timing condition comprises a relative transition rate between a reference node and said output node of said driver amplifier.
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30. A switched-mode amplifier comprising:
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a driver amplifier having an output transistor; and
a switch coupled to the output transistor, the switch operable for switching between first, second and third states and wherein, in the first state, the output transistor is on, in the second state, the output transistor is off, and, in the third state, the output transistor is in an intermediate state between on and off. - View Dependent Claims (31, 32, 33)
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Specification