Circuits and methods for slew rate control and current limiting in switch-mode systems

• US 6,597,240 B1
• Filed: 04/02/2001
• Issued: 07/22/2003
• Est. Priority Date: 04/02/2001
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Walburger, Eric, Melanson, John Laurence
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Khai M.
• Application Number:
  US09/825,443
• Time in Patent Office: 841 Days
• Field of Search: 330/10, 330/207.P, 330/251
• US Class Current: 330/10
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence

Abstract

An apparatus and method for limiting the output current in a switched mode amplifier are implemented. The apparatus includes a driver amplifier configurable for selective operation in one of three modes. The amplifier is operable for transitioning between the first mode and one of the second and third modes in response to a state of an output node of the driver. Bias circuitry, configurable for selective coupling to the driver amplifier is operable for limiting the output current of the amplifier in the first operating mode.

Claims

1. A switched-mode amplifier current control apparatus comprising:

a driver amplifier configurable for selective operation in a first, second and third operating mode; and

a bias circuitry configured for selective coupling to said driver amplifier, said bias circuitry operable for limiting an output current of said driver amplifier in said first operating mode, and wherein said driver amplifier is operable for transitioning from said first operating mode to a selected one of said second and third operating modes in response to a state of an output node of said driver amplifier.

2. The apparatus of claim 1 further comprising a switching circuitry coupled to said bias circuitry, wherein said switching circuitry, in a first state, couples said bias circuitry to said switching amplifier.

3. The apparatus of claim 2 wherein said switching circuitry, in a second state, couples said switching amplifier to a first supply voltage, and in a third state, couples said switching amplifier to a second supply voltage.

4. The apparatus of claim 3 wherein, said driver amplifier includes a pull-up device and a pull-down device, and wherein, in said second state, a first one of said pull-up device and said pull-down device is placed in said second operating mode and a complementary one of said pull-up device and said pull-down device is placed in said third operating mode, and in said third state, the complementary one of said pull-up device and said pull-down device is placed in said third operating mode and the first one of said pull-up device and said pull-down device is placed in said second operating mode.

5. The apparatus of claim 3 further comprising:

a reference signal;

a comparator having a first input coupled to said reference signal and a second input coupled to an output node of said driver amplifier;

a control circuitry coupled to an output of said comparator, said control circuitry selecting said second state in response to a value of said output of said comparator and a predetermined timing condition.

6. The apparatus of claim 5 wherein said reference signal comprises a predetermined reference voltage.

7. The apparatus of claim 5 further comprising reference circuitry, and wherein said reference signal comprises a signal at a reference node of said reference circuitry.

8. The apparatus of claim 7 wherein said reference node comprises a junction of a current source, a drain of a field effect transistor (FET), and a capacitor.

9. The apparatus of claim 5 wherein said predetermined timing condition comprises an expiry of a predetermined delay.

10. The apparatus of claim 5 wherein said predetermined timing condition comprises a relative transition rate between a reference node and said output node of said driver amplifier.

11. The apparatus of claim 2 wherein, in said first state, said bias circuit and said driver amplifier form a current mirror.

12. A current control method comprising the steps of:

switching a bias circuit operable for limiting an output current of an amplifier to an input of said amplifier; and

determining if a voltage at an output node of said amplifier satisfies a predetermined condition.

13. The method of claim 12 further comprising the step of, if said predetermined condition is satisfied, switching on a selected one of a pull-up device and a pull-down device in said one of said pull-up device and said pull-down device selected in response to a value of an input signal.

14. The method of claim 13 further comprising the step of, if said predetermined condition is not satisfied, switching off a selected one of said pull-up device and said pull-down device said one of said pull-up device and said pull-down device selected in response to said value of said input signal.

15. The method of claim 12 wherein said predetermined condition comprises, after an expiry of a predetermined delay, said voltage at said output node having a selected ordering relation with a reference voltage, said ordering relation selected in response to a value of an input signal.

16. The method of claim 15 wherein said ordering relation comprises:

if said value of said input signal is a first value, said voltage at said output node is less than a first reference signal; and

if said value of said input signal is a second value, said voltage at said output node is greater than a second reference signal.

17. The method of claim 12 wherein said predetermined condition comprises, a transition rate of said output node exceeds a transition rate of a reference node.

18. The method of claim 17 wherein said reference node comprises a node of a current source, a drain of a field effect transistor (FET) and a capacitor.

19. An amplifier system comprising:

a digital signal source;

a driver amplifier configurable for selective operation in a first, second and third operating mode; and

a bias circuitry configured for selective coupling to said driver amplifier, said bias circuitry operable for limiting an output current of said driver amplifier in said first operating mode, and wherein said driver amplifier is operable for transitioning from said first operating mode to a selected one of said second and third operating modes in response to a state of an output node of said driver amplifier; and

a pulse width modulator coupled to said digital signal source, an output of said pulse width modulator controlling a duty cycle of said driver amplifier.

20. The system of claim 19 further comprising a switch configured for coupling said bias circuitry to said driver amplifier wherein said switch, in a first state, couples said bias circuitry to said switching amplifier.

21. The system of claim 20 wherein, in said first state, said bias circuit and said driver amplifier form a current mirror.

22. The system of claim 19 wherein said switch, in a second state, couples said switching amplifier to a first supply reference voltage, and in a third state, couples said switching amplifier to a second supply reference voltage.

23. The system of claim 22 wherein, said driver amplifier includes a pull-up device and a pull-down device, and wherein, in said second state, a first one of said pull-up device and said pull-down device is turned on and a complementary one of said pull-up device and said pull-down device is turned off, and in said third state, a the complementary one of said pull-up device and said pull-down device is turned on and the first one of said pull-up device and said pull-down device is turned off.

24. The system of claim 22 further comprising:

a reference signal;

a comparator having a first input coupled to said reference signal and a second input coupled to an output node of said driver amplifier;

control circuitry coupled to an output of said comparator, said control circuitry selecting said second state in response to a value of said output of said comparator and a predetermined timing condition.

25. The system of claim 24 wherein said reference signal comprises a predetermined reference voltage.

26. The system of claim 24 further comprising reference circuitry, and wherein said reference signal comprises a signal at a reference node of said reference circuitry.

27. The system of claim 26 wherein said reference node comprises a junction of a current source, a drain of a field effect transistor (FET), and a capacitor.

28. The system of claim 24 wherein said predetermined timing condition comprises an expiry of a predetermined delay.

29. The system of claim 24 wherein said predetermined timing condition comprises a relative transition rate between a reference node and said output node of said driver amplifier.

30. A switched-mode amplifier comprising:

a driver amplifier having an output transistor; and

a switch coupled to the output transistor, the switch operable for switching between first, second and third states and wherein, in the first state, the output transistor is on, in the second state, the output transistor is off, and, in the third state, the output transistor is in an intermediate state between on and off.

31. The switched-mode amplifier of claim 30 wherein the switch switches between the second state and the third state to initiate a turn-on of the output transistor and switches from the third state to the first state in response to a monitor coupled to an output node of the output transistor.

32. The switched-mode amplifier of claim 31 wherein the monitor coupled to the output node senses output voltage.

33. The switched-mode amplifier of claim 30 wherein the intermediate state comprises a saturation region of a MOSFET drain-source characteristic.