Decoding apparatus and decoding method

• US 6,597,295 B1
• Filed: 10/24/2000
• Issued: 07/22/2003
• Est. Priority Date: 11/01/1999
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Fukuyama, Mariko
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): NGUYEN, KHAI M
• Application Number:
  US09/695,209
• Time in Patent Office: 1,001 Days
• Field of Search: 341/58, 341/59, 341/68, 341/69, 375/287, 375/340, 714/709
• US Class Current: 341/58
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/10203 baseline correction DC correction by choosing codewords of the modulation code G11B20/1426
• CPC Class Codes: G11B 20/10212 compensation for data shift, e.g. pulse-crowding effects
• CPC Class Codes: G11B 20/10296 using the Viterbi algorithm
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 20/1803 by redundancy in data representation
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof
• CPC Class Codes: H03M 7/46 Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind

Abstract

A data-decoding apparatus having bit-detecting section 4. In the apparatus, an RF signal is reproduced from a recording medium and converted to digital data. If the RF signal has a level (amplitude) equal to a comparator level, the bit-detecting section 4 outputs channel-bit data having logic level “0” or “1” in accordance with whether the sum of the amplitudes of the two RF signals respectively preceding and following that RF signal is higher or lower than the comparator level.

Claims

1. A data-decoding apparatus for comparing a logic level of data with a threshold level, thereby generating a decoded bit, said apparatus comprising:

decoded-bit determining means for determining the logic level of the data from the levels of two data items respectively preceding and following the data when the data has a level equal to the threshold level, wherein the decoded-bit determining means sets the decoded bit at a first logic level when the sum of the two data items respectively preceding and following the data is higher than the threshold level.

2. The data-decoding apparatus according to claim 1, wherein the decoded-bit determining means sets the decoded bit at a second logic level when the sum of the two data items respectively preceding and following the data is lower than the threshold level.

3. The data-decoding apparatus according to claim 1, wherein the decoded-bit determining means sets the decoded bit at the first logic level or the second logic level when the sum of the two data items respectively preceding and following the data is equal to the threshold level.

4. The data-decoding apparatus according to claim 1, wherein the data is digital data generated by converting a reproduced, waveform-equalized RF signal by analog-to-digital converting means, the decoded-bit determining means determines whether the decoded bit is the first logic level or the second logic level by comparing the levels of two data items with the threshold level which is a center level of the amplitude of the digital data, and the decoded-bit determining means determines whether the decoded bit is the first logic level or the second logic level by comparing a sum of the two data items with the threshold level when the digital data has a level equal to the threshold level.

5. The data-decoding apparatus according to claim 4, designed for use in a data-reproducing apparatus for reproducing data from a recording medium in which a code is recorded, said code having a minimum length d′

of identical symbols, represented as d′

=d+1, where d is a minimum length of consecutive second logic levels interposed between two first logic levels, said identical symbols having been obtained by NRZI modulation and including a symbol satisfying the condition of d=1.

6. The data-decoding apparatus according to claim 5, wherein the decoded-bit determining means sets the decoded bit at the first logic level when the sum of the two data items respectively preceding and following the data is higher than the threshold level.

7. The data-decoding apparatus according to claim 5, wherein the decoded-bit determining means sets the decoded bit at the second logic level when the sum of the two data items respectively preceding and following the data is lower than the threshold level.

8. The data-decoding apparatus according to claim 5, wherein the decoded-bit determining means sets the decoded bit at the first logic level or the second logic level when the sum of the two data items respectively preceding and following the data is equal to the threshold level.

9. A data-decoding method of decoding a bit by comparing the level of input data with a threshold level, thereby generating a decoded bit, comprising:

determining whether the decoded bit is a first logic level or a second logic level from the levels of two data items respectively preceding and following the input data, when the level of the input data is equal to the threshold level, whereby the method is designed for use in a data-reproducing apparatus for reproducing data from a recording medium in which a code is recorded, said code having a minimum length d′

of identical symbols, represented as d′

=d+1, where d is a minimum length of consecutive second logic levels interposed between two first logic levels, said identical symbols having been obtained by NRZI modulation and including a symbol satisfying the condition of d=1.

10. A data decoding apparatus comprising:

an A/D converter configured to output successive digital data, including a current data, a previous data occurring before the current data, and a following data occurring after the current data; and

a data detector connected to the A/D converter and configured to compare the digital data with a comparator level and output a decoded bit, including

a data corrector configured to output a decoded bit based on values of the preceding data and the following data when the current data is equal to the comparator level, the data corrector being configured to detect a sum of the previous data and the following data and to output as the decoded bit a first logic level when the sum is positive and a second logic level when the sum is negative.