Non-volatile memory with test rows for disturb detection

• US 6,597,609 B2
• Filed: 08/30/2001
• Issued: 07/22/2003
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US09/943,480
• Publication Number:
  US 20030043661A1
• Time in Patent Office: 691 Days
• Field of Search: 365/201, 365/196, 365/185.22, 365/185.29
• US Class Current: 365/201
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.

Claims

1. A non-volatile memory device comprising:

an array of reprogrammable non-volatile memory cells arranged in rows and columns;

a plurality of bit lines coupled to the non-volatile memory cells;

a driver circuit coupled to the plurality of bit lines; and

test rows coupled to the array, wherein the driver circuit comprises first and second bit line drivers located at opposite ends of the array rows, and the test rows comprise first and second pairs of test rows respectively located adjacent to the first and second bit line drivers.

2. The non-volatile memory device of claim 1 wherein the non-volatile memory cells are floating gate transistors.

3. A flash memory device comprising:

an array of floating gate non-volatile memory cells arranged in rows and columns;

a bit line coupled to the non-volatile memory cells;

first and second driver circuits respectively coupled to first and second end regions of the bit line;

a decoder circuit to selectively couple the first and second driver circuits to the bit line; and

first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits.

4. The flash memory device of claim 3 wherein the first and second sets of addressable test rows each comprise two test rows.

5. The flash memory device of claim 3 further comprising a disturb test circuit to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.

6. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells;

X distributed driver circuits coupled to the bit line; and

X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits, wherein X equals two and the two pairs of addressable test rows are located at opposite ends of the bit line.

7. A method of erasing memory cells in a non-volatile memory device comprising:

initiating an erase operation on memory cells located in a first part of an addressable array of memory cells; and

performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation of memory cells located in a second part of the addressable array.

8. The method of claim 7 wherein performing the disturb test operation comprises:

coupling a predefined word line voltage to memory cells located in the test rows; and

determining if the memory cells located in the test rows are activated in response to the predefined word line voltage.

9. The method of claim 7 further comprises performing a data recovery operation on the memory cells located in the second part of the addressable array based upon the disturb test operation on the test rows.

10. The method of claim 7 further comprises performing a data recovery operation on the memory cells located in the test rows based upon the disturb test operation on the test rows.

11. The method of claim 7 wherein the test rows comprise two test rows located on an edge of addressable array of memory cells.

12. The method of claim 7 wherein the memory cells are floating gate transistor memory cells.

13. The method of claim 7 further comprising:

locating the test rows near at least one driver circuit.

14. A method of operating a non-volatile memory device comprising:

initiating an erase operation on a first erase block of memory cells located in an addressable array of memory cells, wherein the array has X erase blocks; and

performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation of memory cells located in remaining X−

1 erasable blocks, wherein the test rows are not located within the X erase blocks.

15. The method of claim 14 wherein the test rows comprise two test rows located on an edge of the X erase blocks.

16. The method of claim 14 further comprises performing a data recovery operation on the remaining X−

1 erasable blocks based upon the disturb test operation on the test rows.

17. The method of claim 14 wherein the memory cells are floating gate transistor memory cells.

18. The method of claim 14 further comprising:

locating the test rows near at least one driver circuit.

19. A method of operating a non-volatile memory system comprising:

initiating an erase operation on memory cells located in a first block of an array of memory cells of a memory device in response to instructions from an external processor;

performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation or a prior operation of memory cells located in additional blocks of the array; and

performing a data recovery operation on the memory cells located in the additional blocks of the array based upon the disturb test operation.

20. The method of claim 19 wherein the test rows comprise two test rows located on an edge of the array of memory cells.

21. The method of claim 19 wherein the memory cells are floating gate transistor memory cells.

22. The method of claim 19 further comprising:

locating the test rows near at least one driver circuit.

23. A memory system comprising:

a processor; and

a non-volatile memory device coupled to the processor and comprising,

an array of floating gate non-volatile memory cells arranged in rows and columns,

a bit line coupled to the non-volatile memory cells,

first and second driver circuits respectively coupled to first and second end regions of the bit line,

a decoder circuit to selectively couple the first and second driver circuits to the bit line, and

first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits.

24. The memory system of claim 23 wherein the first and second sets of addressable test rows each comprise two test rows.

25. The memory system of claim 23 further comprising a disturb test circuit coupled to the test rows to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.

26. A memory device comprising:

an array of memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines; and

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, wherein the first and second driver circuits are located at opposite ends of the plurality of bit lines.

27. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

wherein the first and second driver circuits are activated simultaneously to drive data on the plurality of bit lines.

28. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

wherein the first and second driver circuits are independently activated to drive data on the plurality of bit lines.

29. A memory device comprising:

an array of memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines; and

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, wherein the first and second driver circuits are independently activated to drive data on the plurality of bit lines and wherein an un-activated driver circuit is placed in a tri-state condition.

30. A memory device comprising:

an array of memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines; and

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, further comprising a disturb circuit coupled to the first and second sets of test rows to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.

31. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits;

a third driver circuit electrically coupleable to the plurality of bit lines; and

a third set of test rows coupled to the array and respectively located near the third driver circuit.

32. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows and columns;

a plurality of bit lines coupled to the non-volatile memory cells;

a driver circuit coupled to the plurality of bit lines;

test rows coupled to the array and located near the driver circuit; and

a disturb test circuit to determine if the memory cells of the test rows have been disturbed.

33. A flash memory device comprising:

an array of floating gate non-volatile memory cells arranged in rows and columns;

a bit line coupled to the non-volatile memory cells;

first and second driver circuits respectively coupled to first and second end regions of the bit line;

a decoder circuit to selectively couple the first and second driver circuits to the bit line;

first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits; and

a disturb test circuit to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.

34. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells;

X distributed driver circuits coupled to the bit line;

X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits; and

a disturb test circuit to determine if the memory cells of the X pairs of addressable test rows have been disturbed.