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Non-volatile memory with test rows for disturb detection

  • US 6,597,609 B2
  • Filed: 08/30/2001
  • Issued: 07/22/2003
  • Est. Priority Date: 08/30/2001
  • Status: Active Grant
First Claim
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1. A non-volatile memory device comprising:

  • an array of reprogrammable non-volatile memory cells arranged in rows and columns;

    a plurality of bit lines coupled to the non-volatile memory cells;

    a driver circuit coupled to the plurality of bit lines; and

    test rows coupled to the array, wherein the driver circuit comprises first and second bit line drivers located at opposite ends of the array rows, and the test rows comprise first and second pairs of test rows respectively located adjacent to the first and second bit line drivers.

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