Memory read circuitry

• US 6,597,611 B2
• Filed: 11/15/2002
• Issued: 07/22/2003
• Est. Priority Date: 07/17/2001
• Status: Active Grant

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Desai, Shaishav A., Tawari, Devendra N.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Pham, Ly Duy
• Application Number:
  US10/295,953
• Publication Number:
  US 20030067823A1
• Time in Patent Office: 249 Days
• Field of Search: 365/203, 365/189.08, 365/194, 365/214, 365/220, 365/230.05
• US Class Current: 365/203
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Claims

1. A read circuit on a semiconductor comprising:

a) a precharge input;

b) a first switch, the gate of the first switch coupled to the precharge input, the source of the firs coupled to a voltage source, the drain of the first switch coupled to a local bitline;

c) a first delay element, the input of the first delay element coupled to the precharge input;

d) a second delay element, the input of the second delay element coupled to the output of the first delay element;

e) a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline;

f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source;

g) a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground;

h) a fifth switch, the gate of the fifth switch coupled to the/bitline , the source of the fifth switch coupled to the drain of the third switch, the drain of the fifth switch coupled to the drain of the fourth switch; and

i) a sixth switch, the gate of the sixth switch coupled to the drain of the fifth switch, the drain of the sixth switch coupled to the global bitline, the source of the sixth switch coupled to ground.

2. The read circuit of claim 1, wherein the first switch is a metal oxide semiconductor transistor.

3. The read circuit of claim 1, wherein the first switch is a p-type metal oxide semiconductor transistor.

4. The read circuit of claim 1, wherein the first delay element is an inverter.

5. The read circuit of claim 1, wherein the second delay element is an inverter.

6. The read circuit of claim 1, wherein the third switch is a type metal oxide semiconductor.

7. The read circuit of claim 1, wherein the fourth switch is an n-type metal oxide semiconductor.

8. The read circuit of claim 1, wherein the fifth switch is a p-type metal oxide semiconductor.

9. The read circuit of claim 1, wherein the sixth switch is an n-type metal oxide semiconductor.

10. The read circuit of claim 1, further comprising:

j) a seventh switch, the gate of the seventh switch coupled to the global bitline, the drain of the seventh switch coupled to the gate of the sixth switch, the source of the seventh switch coupled to ground; and

k) an eighth switch, the gate of the eighth switch coupled to the gate of the sixth switch, the source of the eighth switch coupled to the voltage source, the drain of the eighth switch coupled to the first local bitline.

11. The read circuit of claim 10, wherein the seventh switch is an n-type metal oxide semiconductor.

12. The read circuit of claim 10, wherein the eighth switch is a p-type metal oxide semiconductor.

13. The read circuit of claim 10, further comprising:

l) a ninth switch, the gate of the ninth switch coupled to the precharge input, the source of the ninth switch coupled to the voltage source, the drain of the ninth switch coupled to the second local bitline;

m) a tenth switch, the gate of the tenth switch coupled to the gate of the sixth switch, the source of the tenth switch coupled to the voltage source, the drain of the tenth switch coupled to the second local bitline; and

n) an eleventh switch, the gate of the eleventh switch coupled to the second local bitline, the source of the eleventh switch coupled to the drain of the third switch, the drain of the eleventh switch is coupled to the gate of the sixth switch.

14. A computer system containing a central processing unit, the central processing unit containing a read circuit including:

a) a precharge input;

b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to a local bitline;

c) a first delay element, the input of the first delay element coupled to the precharge input;

d) a second delay element, the input of the second delay element coupled to the output of the first delay element;

e) a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline;

f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source;

g) a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground;

h) a fifth switch, the gate of the fifth switch coupled to the(bitline, the source of the fifth switch coupled to the drain of the third switch, the drain of the fifth switch coupled to the drain of the fourth switch; and

i) a sixth switch, the gate of the sixth switch coupled to the drain of the fifth switch, the drain of the sixth switch coupled to the global bitline, the source of the sixth switch coupled to ground.

15. A Dynamic Random Access Memory (DRAM) containing a read circuit including:

a) a precharge input;

b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to a local bitline;

c) a first delay element, the input of the first delay element coupled to the precharge input;

d) a second delay element, the input of the second delay element coupled to the output of the first delay element;

e) a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline;

f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source;

g) a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground;

h) a fifth switch, the gate of the fifth switch coupled to the local bitline, the source of the fifth switch coupled to the drain of the third switch, the drain of the fifth switch coupled to the drain of the fourth switch; and

i) a sixth switch, the gate of the sixth switch coupled to the drain of the fifth switch, the drain of the sixth switch coupled to the global bitline, the source of the sixth switch coupled to ground.