Serial signal transmission apparatus

• US 6,598,102 B1
• Filed: 06/29/2000
• Issued: 07/22/2003
• Est. Priority Date: 06/30/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ninomiya, Ryoji, Nakamura, Nobutaka
• Primary Examiner(s): Lefkowitz, Sumati
• Assistant Examiner(s): Chung-Trans, X.
• Application Number:
  US09/605,992
• Time in Patent Office: 1,118 Days
• Field of Search: 710/100, 710/300, 710/301, 710/302, 710/303, 710/304, 710/105, 710/106, 710/305, 710/306, 710/310, 710/313, 710/314
• US Class Current: 710/100
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

In this invention, serial transmission suitable for signal lines in which a transformer is inserted is realized by using existing differential buffers. Differential output buffers are connected in parallel with each other. A differential signal line pair in which a transformer is inserted is driven by these two differential output buffers. In this case, a voltage between the two lines of the differential signal line pair is determined by a combination of outputs from the two differential output buffers, and three values, i.e., “+V”, “−V”, and “zero”, can be output. By using this ternary data, serial signal transmission based on the bipolar transfer mode can be performed, and serial transmission suitable for the signal lines in which the transformer is inserted can be realized.

Claims

1. An electronic apparatus for transmitting serial data through first and second signal lines in which a transformer is inserted, wherein first and second terminals on a primary side of the transformer are respectively connected to the first and second signal lines, comprising:

a first differential output buffer whose positive and negative output terminals are respectively connected to the first and second signal lines; and

a second differential output buffer whose positive and negative output terminals are respectively connected to the first and second signal lines,

wherein the first and second signal lines are driven by using said first and second differential output buffers to convert each binary data constituting serial data into ternary data including a first state in which a current flows in said transformer in a positive direction, a second state in which a current flows in said transformer in a negative direction, and a third state in which no current flows in said transformer, and the ternary data is output onto the signal line pair.

2. An apparatus according to claim 1, wherein said apparatus further comprises:

a first differential input buffer having a positive or negative signal input terminal and a reference signal input terminal, the positive or negative signal input terminal being connected to one of the first and second signal lines on a secondary side of said transformer; and

a second differential input buffer having a positive or negative signal input terminal and a reference signal input terminal, the positive or negative signal input terminal being connected to the other of the first and second signal lines on the secondary side of said transformer,

wherein a value of the ternary data transmitted through the first and second signal lines are detected by a combination of output signals from said first and second differential input buffers.

3. An apparatus according to claim 2, further comprising means for applying a predetermined bias voltage between the reference signal input terminals of said first and second differential input buffers and the first and second signal lines on the secondary side of said transformer so as to produce potential differences between the reference signal input terminals and the first and second signal lines on the secondary side of said transformer in the third state.

4. An electronic apparatus for connection between buses of computers, comprising:

a signal line pair including first and second signal lines in which a transformer is inserted, wherein first and second terminals on a primary side of the transformer are respectively connected to the first and second signal lines;

means for converting information required for transaction transfer between the buses from parallel data to serial data;

a first differential output buffer whose positive and negative output terminals are respectively connected to the first and second signal lines;

a second differential output buffer whose positive and negative output terminals are respectively connected to the first and second signal lines; and

means for generating input signals to be respectively supplied to said first and second differential output buffers on the basis of each binary data constituting the serial data so as to transmit through the first and second signal lines ternary data including a first state in which a current flows in said transformer in a positive direction, a second state in which a current flows in said transformer in a negative direction, and a third state in which no current flows in said transformer.

5. An apparatus according to claim 4, further comprising:

a first differential input buffer having a positive or negative signal input terminal and a reference signal input terminal, the positive or negative signal input terminal being connected to one of the first and second signal lines on a secondary side of said transformer;

a second differential input buffer having a positive or negative signal input terminal and a reference signal input terminal, the positive or negative signal input terminal being connected to the other of the first and second signal lines on the secondary side of said transformer; and

means for detecting a value of the ternary data transmitted through the first and second signal lines on the basis of a combination of output signals from said first and second differential input buffers, and converting the value into binary data constituting serial data.

6. An apparatus according to claim 5, further comprising means for applying a predetermined bias voltage between the reference signal input terminals of said first and second differential input buffers and the first and second signal lines on the secondary side of said transformer so as to produce potential differences between the reference signal input terminals and the first and second signal lines on the secondary side of said transformer in the third state.

7. An electronic apparatus comprising:

a first differential output buffer whose positive and negative output terminals are respectively connected to first and second signal lines;

a second differential output buffer whose positive and negative output terminals are respectively connected the first and second signal lines; and

means for driving said first and second differential output buffers in response to input binary serial data to set a first state in which a current flows through the first signal line in a first direction, and a current flows through the second signal line in a second direction, a second state in which a current flows through the first signal line in the second direction, and a current flows through the second signal line in the first direction, or a third state in which no current flows through the first and second signal lines.

8. An apparatus according to claim 7, wherein said driving means drives said first and second differential output buffers to set the first state when input serial data has a first value and last input serial data had a second value, the second state when the input serial data has the second value and the last input serial data had the first value, and the third state when the input serial data is identical to the last input serial data.

9. An apparatus according to claim 7, further comprising conversion means connected to said driving means for converting parallel data into binary serial data.

10. An apparatus according to claim 9, further comprising bus interface means connected to said conversion means.

11. An apparatus according to claim 7, further comprising:

a first differential input buffer having a positive signal input terminal, a reference signal input terminal, and an output terminal;

a second differential input buffer having a negative signal input terminal, a reference signal input terminal, and an output terminal; and

means for generating binary serial data in response to outputs from said first and second differential input buffers.

12. An apparatus according to claim 11, further comprising a transformer whose first and second terminals on a secondary side are respectively connected to said positive signal input terminal of said first differential input buffer and said negative signal input terminal of said second differential input buffer.

13. An apparatus according to claim 12, further comprising means for applying a predetermined bias voltage between the reference signal input terminals of said first and second differential input buffers and the first and second terminals on the secondary side of said transformer to produce potential differences between the reference signal input terminals and the first and second terminals on the secondary side of said transformer when no current flows on a primary side of said transformer.

14. An apparatus according to claim 12, wherein said transformer is a pulse transformer.

15. An electronic apparatus comprising:

a first differential input buffer having a positive signal input terminal, a reference signal input terminal, and an output terminal;

a second differential input buffer having a negative signal input terminal, a reference signal input terminal, and an output terminal;

means for generating binary serial data in response to outputs from said first and second differential input buffers; and

a transformer whose first and second terminals on a secondary side are respectively connected to said positive signal input terminal of said first differential input buffer and said negative signal input terminal of said second differential input buffer.

16. An apparatus according to claim 15, further comprising means for applying a predetermined bias voltage between the reference signal input terminals of said first and second differential input buffers and the first and second terminals on the secondary side of said transformer so as to produce potential differences between the reference signal input terminals and the first and second terminals on the secondary side of said transformer when no current flows on a primary side of said transformer.

17. An apparatus according to claim 15, wherein said transformer is a pulse transformer.

18. An electronic apparatus comprising:

a terminal receiving binary serial data;

means for encoding said binary serial data into ternary data; and

means for outputting said encoded ternary data,

wherein the outputting means have a first and a second output terminals to output the ternary data with at least three states including a first state in which a voltage of the first output terminal is higher than a voltage of the second output terminal, a second state in which a voltage of the second output terminal is higher than a voltage of the first output terminal, and a third state in which a voltage of the first output terminal and a voltage of the second output terminal are approximately same.

19. An electronic apparatus comprising:

a binary data source;

transformer whose first and second terminals on a primary side are respectively connected to first and second lines;

a terminal receiving binary serial data from said binary data source;

means for encoding said binary serial data into ternary data;

first means for outputting said encoded ternary data through the first and second signal lines to said transformer;

means for receiving said ternary data from said transformer;

means for decoding said ternary data into said binary data; and

second means for outputting said decoded binary data,

wherein said first outputting means outputs said ternary data with at least three states including a first state in which a current flows in said transformer in a negative direction, and a third state in which a current flow in said transformer is prevented.